Marvell Asia Pte., Ltd.

Advanced Micro Devices Corporation

Ati Technologies Ulc

Cavium, Inc.

Marvell Semiconductor, Inc.

David Da Wei Lin

Anwar Kashem

Ronald L Pettyjohn

Gershom Birk

Pouya Najafi Ashtiani

In accordance with described techniques for read gate training and tracking, a computing device includes a memory system (e.g., dynamic random access memory (DRAM)) that receives a memory read operation which includes a memory clock that correlates to a physical layer (PHY) clock. The computing device includes a PHY that receives a return data signal from the memory system, where the return data signal includes a returned data strobe that is out-of-phase with respect to the PHY clock. The computing device includes training logic that utilizes edge detection to determine an unknown clocking phase of the returned data strobe with respect to the PHY clock. The computing device also includes tracking logic that utilizes the edge detection to detect a signal drift of the delay signal with respect to the returned data strobe and compensate for the drift.

Read gate training and tracking

Systems and methods of write deskew training for &#xd7;4 mode memory control interface configurations. Write leveling logic in the memory controller is adjusted to obtain a write leveling setting for delaying both first and second strobe signals associated with a byte. The adjustment is based on feedback of first set of bits of a byte and irrespective of the feedback of the second set of bits of the byte. The write leveling logic is then anchored at the write leveling setting, and a deskew delay line for the second strobe signal is adjusted to obtain a first deskew setting based on the feedback of the second set of bits. Thus, in write operations, the write leveling setting can be common within the byte even the two strobe signals are transmitted to or received from two different memory storage devices.

Write and read common leveling for 4-bit wide drams

System and method of write deskew training for &#xd7;4 mode memory control interface configurations. Write leveling logic in the memory controller is adjusted to obtain a write leveling setting for delaying both first and second strobe signals associated with a byte. The adjustment is based on feedback of first set of bits of a byte and irrespective of the feedback of the second set of bits of the byte. The write leveling logic is then anchored at the write leveling setting, and a deskew delay line for the second strobe signal is adjusted to obtain a first deskew setting based on the feedback of the second set of bits. Thus, in write operations, the write leveling setting can be common within the byte even the two strobe signals are transmitted to or received from two different memory storage devices.

Write and read common leveling for 4-bit wide DRAMS

System and method of read deskew training for &#xd7;4 mode memory control interface configurations. A read deskew training process includes aligning the two strobe signals serving one byte before deskewing the data bits against their corresponding strobe signals. A deskew setting of a variable delay line associated with the second strobe signal is adjusted to align the second strobe signal with reference to the first strobe signal. By aligning the two strobe signals with respect to each other, the read leveling settings can be common within the byte even the two DQS signals are transmitted to or received from two different memory storage devices.

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Westborough, MA, United States of America

David Da Wei Lin