Sunpower Corporation

Maxeon Solar Pte. Ltd.

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David D Smith

Peter John Cousins

Gabriel Harley

Taeseok Kim

Tim Dennis

Ann P Waldhauer

Seung Bum Rim

Richard M Swanson

Venkatasubramani Balu

Douglas H Rose

Michael C Johnson

Michael T Morse

Denis De Ceuster

Scott Harrington

Kieran Mark Tracy

Timothy Weidman

Matthieu Moors

Staffan Westerberg

Yu-Chen Shen

Neil Kaminar

Richard Hamilton Sewell

Bo Li

Taiqing Qiu

Jane Manning

Michael Cudzinovic

Steven E Molesa

Paul Loscutoff

David Aaron Randolph Barkhouse

Joseph Frederick Behnke

Thomas Pass

Sung Dug Kim

Hung-Ming Wang

Sheng Sun

Périne Jaffrennou

Marius M Bunea

Jens-Dirk Moschner

Vikas Desai

Russelle De Jesus Tabajonda

Pongsthorn Uralwong

Asnat Masad

Xiuwen Tu

Junbo Wu

Keith R McIntosh

Michael J Defensor

Michael Shepherd

Bharatkumar Gamanlal Mehta

Jeffrey El Cotter

William P Mulligan

Hsin-Chiao Luan

Xi Zhu

Genevieve A Solomon

Andy Luan

David D Cramer

Helen Liu

Brenda Pagulayan Malgapu

Joseph Ramirez

Richard Sewell Hamilton

Donald L Purvis

Douglas L Walton

Princess Carmi Tomada

Kim Taeseok

A solar cell, and methods of fabricating said solar cell, are disclosed. The solar cell can include a substrate having a light-receiving surface and a back surface. The solar cell can include a first semiconductor region of a first conductivity type disposed on a first dielectric layer, wherein the first dielectric layer is disposed on the substrate. The solar cell can also include a second semiconductor region of a second, different, conductivity type disposed on a second dielectric layer, where a portion of the second thin dielectric layer is disposed between the first and second semiconductor regions. The solar cell can include a third dielectric layer disposed on the second semiconductor region. The solar cell can include a first conductive contact disposed over the first semiconductor region but not the third dielectric layer. The solar cell can include a second conductive contact disposed over the second semiconductor region, where the second conductive contact is disposed over the third dielectric layer and second semiconductor region. In an embodiment, the third dielectric layer can be a dopant layer.

Solar cells having hybrid architectures including differentiated p-type and n-type regions

Approaches for the foil-based metallization of solar cells and the resulting solar cells are described. In an example, a solar cell includes a substrate. A plurality of alternating N-type and P-type semiconductor regions is disposed in or above the substrate. A conductive contact structure is disposed above the plurality of alternating N-type and P-type semiconductor regions. The conductive contact structure includes a plurality of metal seed material regions providing a metal seed material region disposed on each of the alternating N-type and P-type semiconductor regions. A metal foil is disposed on the plurality of metal seed material regions, the metal foil having anodized portions isolating metal regions of the metal foil corresponding to the alternating N-type and P-type semiconductor regions.

Foil-based metallization of solar cells

A method of fabricating a solar cell is disclosed. The method can include forming a dielectric region on a surface of a solar cell structure and forming a metal layer on the dielectric layer. The method can also include configuring a laser beam with a particular shape and directing the laser beam with the particular shape on the metal layer, where the particular shape allows a contact to be formed between the metal layer and the solar cell structure.

Contacts for solar cells

A solar cell, and methods of fabricating said solar cell, are disclosed. The solar cell can include a first emitter region over a substrate, the first emitter region having a perimeter around a portion of the substrate. A first conductive contact is electrically coupled to the first emitter region at a location outside of the perimeter of the first emitter region.

Solar cells having hybrid architectures including differentiated p-type and n-type regions with offset contacts

The formation of solar cell contacts using a laser is described. A method of fabricating a back-contact solar cell includes forming a poly-crystalline material layer above a single-crystalline substrate. The method also includes forming a dielectric material stack above the poly-crystalline material layer. The method also includes forming, by laser ablation, a plurality of contacts holes in the dielectric material stack, each of the contact holes exposing a portion of the poly-crystalline material layer; and forming conductive contacts in the plurality of contact holes.

Solar cell having conductive contacts in alignment with recast signatures

A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched.

Backside contact solar cells with separated polysilicon doped regions

Solar cells having emitter regions composed of wide bandgap semiconductor material are described. In an example, a method includes forming, in a process tool having a controlled atmosphere, a thin dielectric layer on a surface of a semiconductor substrate of the solar cell. The semiconductor substrate has a bandgap. Without removing the semiconductor substrate from the controlled atmosphere of the process tool, a semiconductor layer is formed on the thin dielectric layer. The semiconductor layer has a bandgap at least approximately 0.2 electron Volts (eV) above the bandgap of the semiconductor substrate.

Solar cell having an emitter region with wide bandgap semiconductor material

A bypass diode can include a first conductive region of a first conductivity type disposed above a substrate of a solar cell and a second conductive region of a second conductivity type disposed above the first conductive region. The bypass diode can include a thin dielectric region disposed directly between the first and second conductive regions.

Built-in bypass diode

Methods of fabricating solar cell emitter regions using substrate-level ion implantation, and resulting solar cells, are described. In an example, a method of fabricating a solar cell involves forming a lightly doped region in a semiconductor substrate by ion implantation, the lightly doped region of a first conductivity type of a first concentration. The method also involves forming a first plurality of dopant regions of the first conductivity type of a second, higher, concentration by ion implantation, the first plurality of dopant regions overlapping with a first portion of the lightly doped region. The method also involves forming a second plurality of dopant regions by ion implantation, the second plurality of dopant regions having a second conductivity type of a concentration higher than the first concentration, and the second plurality of dopant regions overlapping with a second portion of the lightly doped region and alternating with but not overlapping the first plurality of dopant regions.

Solar cell emitter region fabrication using substrate-level ion implantation

Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.

Tri-layer semiconductor stacks for patterning features on solar cells

Aligned metallization approaches for fabricating solar cells, and the resulting solar cells, are described. In an example, a solar cell includes a semiconductor layer over a semiconductor substrate. A first plurality of discrete openings is in the semiconductor layer and exposes corresponding discrete portions of the semiconductor substrate. A plurality of doped regions is in the semiconductor substrate and corresponds to the first plurality of discrete openings. An insulating layer is over the semiconductor layer and is in the first plurality of discrete openings. A second plurality of discrete openings is in the insulating layer and exposes corresponding portions of the plurality of doped regions. Each one of the second plurality of discrete openings is entirely within a perimeter of a corresponding one of the first plurality of discrete openings. A plurality of conductive contacts is in the second plurality of discrete openings and is on the plurality of doped regions.

Aligned metallization for solar cells

Solar cells having hybrid architectures including differentiated P-type and N-type regions

A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.

Hybrid polysilicon heterojunction back contact cell

Growing community of inventors

Campbell, CA, United States of America

David D Smith