Bae Systems Information and Electronic Systems Integration Inc.

Other

David D Moser

Daniel L Stanley

Michael J Frack

Tate J Keegan

Christopher N Peters

Sheldon L Grass

Warren E Parkhurst

Joshua C Schabel

Mark R Shaffer

Bin Li

Jason F Ross

Richard J Ferguson

Nicholas J Chiolino

Daniel Pirkl

Patrick Fleming

Elizabeth J Williams

Landon J Caley

David Bostedo

Brian A Saari

Umair Aslam

Stephen A Chadwick

Angelica Sunga

Jason T Dowling

Kevin Linger

A secure system includes a data port, a network on chip (NoC) module, a processor communicatively coupled to the NoC module, a communication interface operatively coupled to the processor and to the data port, an electronic field-programmable gate array (eFPGA) configuration module operatively coupled to the NoC module, and a clock operatively coupled to the NoC module. In a first modality, the communication interface is at least partially disabled. In a second modality, the communication interface is at least partially disabled, boundary scan operations are disabled, a RESET signal is held in a constant state, and/or redacted code is rendered inoperable. In a third modality, the communication interface is at least partially enabled to send and receive commands and data via the data port, the boundary scan operations are enabled, the RESET signal is not held in the constant state, and/or the redacted code is operable.

Secure semiconductor and system design

A system that includes a plurality of encapsulation blocks having a plurality of digital signal processing (DSP) blocks provided with preconfigured logic functions and a plurality of pacing control networks operatively connected with the plurality of DSP blocks. The system also includes a streaming cross bar operatively connected with each encapsulation block of the plurality of encapsulation blocks. Each encapsulation block of the plurality of encapsulation blocks includes a DSP block of the plurality of DSP blocks and a pacing control network of the plurality of the pacing control networks. Each DSP block of the plurality of DSP blocks is independently and separately connected with the streaming cross bar via the plurality of pacing control networks.

DSP eco system scalable with obfuscation

An encapsulation block for a digital signal processing (DSP) block. The encapsulation block includes DSP block having an input terminal, an output terminal, and an input clock. The encapsulation block also includes pacing control network operatively connected with the input terminal, the output terminal, and the input clock of the DSP block. The input terminal of the DSP block is configured to receive a samples-in data stream inputted at a predefined clock period defined by the input clock. The output terminal of the DSP block is configured to receive a samples-out data stream outputted at a predefined paced parameter. The pacing control network is configured to control data flow at the samples-in data stream and the samples-out data stream independently of the DSP block.

DSP encapsulation

Techniques are provided for a radiation hardened memory system. A memory system implementing the techniques according to an embodiment includes a redundancy comparator configured to detect differences between data stored redundantly in a first memory, a second memory, and a third memory. The redundancy comparator is further configured to identify a memory error based on the detected differences. The memory system also includes an error collection buffer configured to store a memory address associated with the memory error, and a memory scrubber circuit configured to overwrite, at the memory address associated with the memory error, erroneous data with corrected data. The corrected data is based on a majority vote among the three memories. The memory system further includes a priority arbitrator configured to arbitrate between the memory scrubber overwriting and functional memory accesses associated with software execution performed by a processor configured to utilize the memory system.

Triple modular redundancy (TMR) radiation hardened memory system

A clock phase control circuit includes a clock input gate module, first and second shift register divider modules, and a multiplexer. The clock input gate module is configured to produce, based on an oscillating input clock signal, first and second intermediate clock signals. The first shift register divider module is configured to produce at least one first phase clock signal based on the first intermediate clock signal, where the at least one first phase clock signal has a different frequency than the first intermediate clock signal. The second shift register divider module is configured to produce at least one second phase clock signal based on the second intermediate clock signal, where the at least one second phase clock signal has a different frequency than the second intermediate clock signal. The multiplexer is configured to produce an output clock signal by selecting one of the first or second phase clock signals.

Clock phase control

A flip-flop circuit is disclosed. The flip-flop circuit includes a single-input inverter, a dual-input inverter, a single-input tri-state inverter, a dual-input tri-state inverter, and two single-event transient (SET) filters. The single-input tri-state inverter receives an input signal D. The dual-input tri-state inverter includes a first input, a second input and an output, wherein the first input receives output signals from the dual-input inverter and the second input receives output signals from the dual-input inverter via the first SET filter. The output of the dual-input tri-state inverter sends output signals to a first input of the dual-input inverter and a second input of the dual-input inverter via the second SET filter. The single-input inverter receives inputs from the dual-input inverter to provide an output signal Q for the flip-flop circuit.

Radiation-hardened D flip-flop circuit

An IC design enhancing tool for automatically reviewing and environmentally hardening an IC design layout. The IC design enhancing tool may be realized, for example, in software that scans through an IC netlist generated by an electronic design automation (EDA) tool and replaces components that are not compliant with one or more hardening criteria. The newly created netlist can then be re-checked by the EDA tool and an iterative process takes place between the EDA tool and the IC design enhancing tool until the final design layout is fully compliant for a given environment. Interrogation of the IC design layout involves determining if at least a portion of the hardware layout netlist meets one or more predetermined hardening criteria. If it does not, then one or more of the hardware components are replaced using one or more predefined hardened components.

Method for radiation hardening of integrated circuits

A scannable-latch random access memory (SLRAM) is disclosed. The SLRAM includes two rows of memory cells. The SLRAM includes a functional data input, a scan data input, a first and second functional data outputs, a scan data output, and a scan enable. The functional data input is connected to a first memory cell in a first and second rows of memory cells. The scan data input is connected to the first memory cell in the first or second row of memory cells. The first and second functional data outputs are connected to a last memory cell in the first and second row of memory cells, respectively. The scan data output is connected to the last memory cell in the first or second row of memory cells. The scan enable allows data to be output from the scan data output or the first and second functional data outputs.

Scannable-latch random access memory

A system and method for controlling pulse width for electronic devices in real time is disclosed. The system includes a Digital Pulse Width Modulator (DPWM), a real time calibration circuit and a delay line circuit. The real time calibration circuit is configured to ensure proper fractional delay is applied to yield correct duty cycle of the DPWM. The delay line circuit comprising a multiplexer delay line with built in decoders, modulates the pulse width for fractional clock cycle delay.

Digitally controlled pulse width modulator utilizing real time calibration

A cathodic protection system for protecting a metallic structure (16,74) from corrosion caused by current flowing between the structure and surrounding environment includes a non-ionized metal anode (18) which exists in a liquid state at the particular pressure and temperature at its location in a hole (20) in the earth. The liquid anode (18) is composed of a metal having a specific gravity greater than 10 and a molecular weight greater than, or equal to, 100. In a preferred embodiment, it is mercury. The amount of liquid anode can be adjusted to regulate the density of electrical current emanating from the anode and the hole in which the anode is located includes a measuring system (46) for monitoring the quantity of liquid anode (18) in the earth hole.

Corrosion protection anode

A cathodic protection system for protecting a metallic structure (16, 74) from corrosion caused by current flowing between the structure and surrounding environment includes a non-ionized metal anode (18) which exists in a liquid state at the particular pressure and temperature at its location in a hole (20) in the earth. The liquid anode (18) is composed of a metal having a specific gravity greater than 10 and a molecular weight greater than, or equal to, 100. In a preferred embodiment, it is mercury. The amount of liquid anode can be adjusted to regulate the density of electrical current emanating from the anode and the hole in which the anode is located includes a measuring system (46) for monitoring the quantity of liquid anode (18) in the earth hole.

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Haymarket, VA, United States of America

David D Moser