Delco Electronics Corporation

Delphi Technologies, Inc.

David D Moller

Philip K Schneider

Salvador A Canales

Ashraf Kamal Kamel

Terrell Anderson

Oscar M Alcantara

Larry R Hach

Gordon D Cheever, Jr

Robert J Berg

Dennis W Berryman

Robert R McConnell

Edward L Hale

James B Archibald

A direct fuel injection control for an internal combustion engine includes first and second controllers. The first controller has a microprocessor and generates injection timing and duration signals on injector select lines. The second controller is a state machine including injector controls that receive the injection timing and duration signals and control injector current according to sets of injector current profile defining parameters received from the first controller on a serial bus and stored in register sets in the second controller. The second controller includes switching apparatus that can quickly change the connection of each injector control between different register sets to select different injector current profiles in successive injection pulses. Several alternative ways of providing register select signals are disclosed, and these may be incorporated in the same second controller for selection by the first controller.

Direct fuel injection control with variable injector current profile

A system and method is provided for improved monitoring and controlling of mechanically commutated DC motors. The system and method include DC motors, pulse-count driver circuitry for driving the motors, motor position sensing circuitry, and motor control circuitry. The system and method provide for improved motor current waveform sensing that is able to effectively reject false brake pulses, avoid erroneous processing due to fluctuating battery voltage levels, and reduce the sensitivity to variations in motor current signals due to dynamic motor load, manufacturing variation, system aging, temperature, brush bounce, EMI, and other factors. The system and method also include an improved ability to multiplex additional external motor drivers to the motor control circuitry, select between sequential and simultaneous drive modes using an SPI bit, and monitor the system controller for an error condition and simultaneously driver motors in response to the error condition.

Method of selectable simultaneous/sequential motor drive in a multiple drive circuit including failure detection

Position detection and external driver multiplexing system for DC motors

A system and method is provided for improved monitoring and controlling of mechanically commutated DC motors. The system and method include DC motors, pulse-count driver circuitry for driving the motors, motor position sensing circuitry, and motor control circuitry. The system and method provide for improved motor current waveform sensing that is able to effectively reject false brake pulses, avoid erroneous processing due to fluctuating battery voltage levels, and reduce the sensitivity to variations in motor current signals due to dynamic motor load, manufacturing variation, system aging, temperature, brush bounce, EMI, and other factors. The system and method also include an improved ability to multiplex additional external motor drivers to the motor control circuitry, select between sequential and simultaneous drive modes using an SPI bit, and monitor the system controller for an error condition and drive the connected motors in response to the error condition.

Voltage-sensitive oscillator frequency for rotor position detection scheme

Method of brake pulse rejection in commutation pulse detection circuits

A slew rate control system for a circuit includes a temperature sensitive device generates a temperature signal. A temperature dependent current source generates a first current source signal. A slew rate controller activates in response to the temperature signal when the temperature exceeds a first threshold. The slew rate controller then generates a slew rate control signal by adjusting slew rate as a function of the temperature signal. The slew rate controller then activates the temperature dependent current source in response to the slew rate control signal.

Dynamic on chip slew rate control for MOS integrated drivers

A circuit for converting an analog signal to a PWM signal samples an amplitude of the analog signal at first sampling rate and a second slower sampling rate, and produces corresponding first and second signals. A comparison signal defines a first state when the first signal is greater than the second signal, and otherwise defines a second opposite state. The PWM signal switches from a first signal level to a second signal level when the comparison signal switches from the first state to the second state only if the comparison signal thereafter remains in the second state for a specified delay period, and the PWM signal switches from the second signal level to the first signal level when the comparison signal switches from the second state to the first state only if the comparison signal thereafter remains in the first state for the delay period.

Circuit for converting an analog signal to a PWM signal

A voltage boost circuit having dual voltage outputs and a single input receives a DC voltage from an external source. The input voltage is boosted to provide a constant voltage at the first output at a level higher than the voltage input and to provide a constant voltage output at the second output. A switch is coupled to the output of the inductor for controlling the current flow to the second output.

Dual output voltage boost circuit

A transmitter for a differential serial data communication bus incorporating the CAN format includes features for minimizing radiated emissions. The transmitter includes a second order input filter for establishing a slew rate of pulses edges and for rounding corners, a first amplifier for attenuating and level shifting the filtered input to produce a first bus output, and a second amplifier coupled to the first bus output for producing a second bus output mirroring the first. The second amplifier has a high unity gain frequency and a closed loop configuration, both for minimizing phase differential of the two outputs.

Balanced phase data bus transmitter

A voltage boost circuit having a voltage output and a single input receives a DC voltage from an external source which is fed to an inductor. The input voltage is boosted to provide a constant voltage at the output at a level higher than the voltage input. A switch is coupled to the output of the inductor for controlling current through the inductor to induce a boosted voltage across the inductor.

Voltage boost circuit

In a preferred embodiment, a multi-configurable output driver, including: first circuitry to provide driving current to an inductive load; the first circuitry being configurable, without the addition or rearrangement of components, in at least two different output topographies; and second circuitry to configure the first circuitry in a selected one of the at least two different output topographies in response to input signals.

Externally multi-configurable output driver

In a preferred embodiment, a multi-configurable output driver, including: circuit apparatus to provide driving current to an inductive load; and the circuit apparatus being configurable, without the addition or rearrangement of components, in at least two different output topographies.

Multi-configurable output driver

A boost circuit effects increasing current flow through an inductor and a switch when the switch is closed, and then, when the switch is open, directs the inductor current through a diode to charge a storage capacitor at the output. A logic circuit operates the switch. The switch is controlled on by sensing low current flow in the capacitor and off by sensing high current flow in the switch, so that inductor current is continuous.

Self clocking, variable frequency boost circuit

A class 2 or UART data communication bus is subject to disruption by induce high frequency currents because of an impedance mismatch between a passive pull-up or pull-down resistor and a lower impedance active current sourcing or sinking stage. An impedance reduction circuit across the passive resistor balances the impedance in the presence of high frequency noise. The impedance reduction circuit is operative when it senses a bus line voltage slew rate greater than that caused by data pulses and a voltage change greater than one diode drop.

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Westfield, IN, United States of America

David D Moller