Intel Corporation

David D Lent

Zohar Bogin

Ashish S Gadagkar

Tuong P Trieu

Narendra S Khandekar

James S Coke

Ajay V Bhatt

Wishwesh Anil Gandhi

Sathyamurthi Sadhasivan

Jeffrey L Rabe

Vincent E VonBokern

Dahmane Dahmani

Santanu Maitra

Stephen T Rowland

Daniel J Dunn

Mitchell W Dale

Stan Graham

Jacob Guerra

Peter Robles

Dave Smyth

Methods of protecting fruit crops from flying insect pests and of repelling flying insects using aromatic amide compounds are disclosed. The methods apply the compounds to various surfaces, such as the fruit crops, the ground or structures adjacent to the fruit crops, or an object, article, human skin or animal. The compounds have the formula RCH—C(═O)—N(Cy), where RCHis a substituted phenyl group, each R group is independently C-Calkyl, substituted C-Calkyl, (substituted) C-Caryl, C-Calkoxy, C-Caryloxy, halogen, nitro, cyano, cyanate, isocyanate, nitroso, C-Calkylthio, phenylthio, (halogen-substituted) C-Calkylsulfonyl, phenylsulfonyl, tolylsulfonyl, amino, mono- or di-C-Calkylamino, diphenylamino, di-C-Calkylamido, formyl, C-Cacyl, or C-Calkoxycarbonyl; x is an integer of 1 to 5; x+y=5; Cy is a C-C(substituted) alkadiyl, a C-C(substituted) alkenediyl, or a (substituted) diyl of the formula —(CHCH)—O—(CHCH)—, —(CHCH)—NR'—(CHCH)— or —(CHCH)—S—(CHCH)— that, along with the amide N atom, forms a non-aromatic cyclic group; and R′ is C-Calkyl, substituted C-Calkyl, (substituted) C-Caryl, or (substituted) benzyl.

Methods of controlling crop pests using aromatic amide insect repellents, methods of making aromatic amide insect repellents, and novel aromatic amide insect repellents

A computer system that includes a host processor (HP), a system memory (SM), and a host bridge coupled to the HP and SM is provided. The host bridge asserts a first read request to the SM and, prior to availability of snoop results in connection with the first read request, the host bridge asserts a following second read request to the SM.

Speculative request pointer advance for fast back-to-back reads

A computer system is provided. The computer system includes a host processor (HP), a system memory (SM), and an input/output (I/O) master device to perform a read of a continuous stream of data to the SM. The computer system also includes a bridge coupled to the HP, SM, and I/O master device. The bridge reads ahead to the SM when the I/O master device reads a continuous stream of data from the SM. The bridge aborts read ahead accesses to the SM, prior to an access commit point to the SM, responsive to disengagement of the I/O master device.

Abort of DRAM read ahead when PCI read multiple has ended

In a bus resource having an outbound pipe for processing both non-posted and posted transactions in a FIFO manner, a rejected non-posted transaction at the head of the outbound pipe is moved aside and into an auxiliary buffer to avoid a potential blockage of the outbound pipe. The auxiliary buffer is for holding transaction information and return data of the rejected non-posted transaction. The rejected transaction is eventually completed from the auxiliary buffer as determined by an arbiter.

Avoiding deadlock by storing non-posted transactions in an auxiliary buffer when performing posted and non-posted bus transactions from an outbound pipe

An arbiter comprising logic circuitry configured to delay granting bus ownership to an agent X in response to receiving a first signal which indicates that a device coupled to the bus is not available to service transactions directed at the device over the bus. For instance, the device may be a bridge and the grant is delayed if an inbound pipe of the bridge is full. The arbiter may provide a borrowed grant to an outbound pipe of the device for performing a transaction on the bus while waiting for an inbound pipe of the device to become available.

Avoiding livelock when performing a long stream of transactions

An embodiment of the invention is directed at a bridge having an outbound pipe for buffering transaction information and data being transported from various devices to a bus. The bridge has an arbiter for granting requests associated with these devices to access the outbound pipe for transferring the transaction information and data into the pipe. The bridge generates a reject signal in response to an initial request associated with an initial transaction from a first one of the devices if the outbound pipe is unavailable to accept further transaction information or data. The bridge has response control logic for generating a retry response for the initial transaction in response to the reject signal. The bridge is able to assert a stamp signal in response to the reject signal. The arbiter in response to the stamp being asserted waits, without granting any other lower priority requests to access the outbound pipe, until a subsequent transaction from the first device makes progress.

Arbitration methods to avoid deadlock and livelock when performing transactions across a bridge

A computer system comprises a direct memory access (DMA) transfer unit and a plurality of DMA devices coupled by an external bus. The DMA transfer unit effectuates DMA transfers for the plurality of DMA devices. The DMA transfer unit contains a DMA controller, a bus arbiter, and a bus controller. The DMA controller and the bus controller generate a two-clock cycle DMA transfer. To effectuate a two-clock cycle DMA transfer, a requesting DMA device sets-up a DMA transfer with the DMA controller such that a DACK# signal is asserted during a first clock period. During a second clock period, the DMA controller sets-up the memory address. During a third clock period, the bus controller transitions a command signal on the external bus. Upon assertion of the command signal, valid data is asserted on the external bus. For demand and block mode operations, additional DMA transfers are executed in a two-clock cycle DMA transfer. The DMA controller and the bus controller also generate a three-clock cycle DMA transfer.

Method and apparatus for fast DMA transfer on an industry standard

A direct memory access (DMA) circuit includes a first register for storing an address for the transfer of data, apparatus for transferring data at sequential addresses beginning at the address in the first register until all data at sequential addresses has been transferred, a second register for storing a beginning address for a list of addresses, and a state machine which responds to the completion of a transfer of data at sequential addresses beginning at the address in the first register and an indication that more data is to be transferred to transfer an address from the list at the address in the second register to the first register and causes the apparatus for transferring data to commence.

Implementing scatter/gather operations in a direct memory access device

A semiconductor component is described which directs transmission of data. The component comprises of a decoder device coupled to said first memory device capable of decoding an address of said data in said first format using said stored address in said first memory device. The component also comprises a translator device coupled to said second memory device capable of transmitting said address of said data in said second format corresponding to said address of said data in said first format, wherein the second format contains the same amount of information as the first format.

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Placerville, CA, United States of America

David D Lent