Intel Corporation

David D Donofrio

Andrew M Volk

Robert R Fulton

Chinnugounder Senthilkumar

Steve S Simoni

Michael D Piorun

Ping Tak Tang

Michael K Dwyer

Xuye Li

An embodiment of the present invention is a technique to perform floating-point operations for vector processing. An input queue captures a plurality of vector inputs. A scheduler dispatches the vector inputs. A plurality of floating-point (FP) pipelines generates FP results from operating on scalar components of the vector inputs dispatched from the scheduler. An arbiter and assembly unit arbitrates use of output section and assembles the FP results to write to the output section.

Scalable parallel pipeline floating-point unit for vector processing

An embodiment of the present invention is a technique to perform floating-point operations. A floating-point (FP) squarer squares a first argument to produce an intermediate argument. The first and intermediate arguments have first and intermediate mantissas and exponents. A FP multiply-add (MAD) unit performs a multiply-and-add operation on the intermediate argument, a second argument, and a third argument to produce a result having a result mantissa and a result exponent. The second and third arguments have second and third mantissas and exponents, respectively.

Enhanced floating-point unit for extended functions

An apparatus, method, and system for performing an enhanced fused multiply-add operation is disclosed. In one embodiment, an apparatus includes an exponent unit. The exponent unit includes a first adder to generate Swhere Sis the sum of an integer k, the exponent of a floating point value A, and the exponent of a floating point value B. The exponent unit also includes a comparator to generate Ewhere Eis the greater of Sand the exponent of a floating point value C. The apparatus also includes a partial multiplier, a shifter, and a second adder. The partial multiplier generates the partial products of the mantissas of A and B. The shifter aligns the partial products and the mantissa of C, based on EThe second adder adds the aligned partial products and the mantissa of C. The apparatus is able to generate not only (A*B+C), but is enhanced to also be able to generate (2*A*B+C) and the closest integer to (2*A*B) in two's complement or floating point format.

Enhanced fused multiply-add operation

According to one embodiment, an integrated circuit (IC) is disclosed. The IC includes a package, a die mounted within the package, circuit components mounted on the die, and a voltage regulator mounted on the die to supply power to the circuit components.

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Benicia, CA, United States of America

David D Donofrio