Texas Instruments Corporation

David D Briggs

Fernando D Carvajal

David Alexander Grant

Taylor R Efland

Charvaka Duvvury

Chin-Yu Tsai

Dale J Skelton

Ramanathan Ramani

Roy Alan Hastings

Gabriel Alfonso Ricon-Mora

Buddhika J Abesingha

Mark Pulkin

Chao-Chih Chiu

Ayesha I Mayhugh

Fred Carvajal

A power integrated circuit architecture ( ) having a high side transistor ( ) interposed between a control circuit ( ) and a low side transistor ( ) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region ( ) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring ( ) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays ( ) partitioned by at least one deep n-type region ( ), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.

Line self protecting multiple output power IC architecture

A structure and method of minimizing package-shift effects in integrated circuits is implemented by using a thick metallic overcoat applied after the deposition and patterning of the conventional insulating protective overcoat. The metallic overcoat most preferably comprises a layer of electrolytically deposited copper approximately 15 &mgr;m thick that is patterned to provide for electrically independent regions; but an unbroken area of the metallic overcoat is left over any sensitive analog circuitry, such as a bandgap reference circuit. The thick metallic coating, in addition to minimizing package-shift effects, is also useful as a low-resistance routing layer. The metallic overcoat is sufficiently thin to allow low-profile packaging. The method employs a conductive overcoat that is significantly thin compared to conventional insulating conformal overcoats.

Semiconductor device which minimizes package-shift effects in integrated circuits by using a thick metallic overcoat

The low voltage to high voltage level shifter has falling-edge 1-shot circuits and coupled to the outputs OUT and OUT_B of cross gate-connected transistors and and pull-down transistors and . The falling-edge 1-shot circuits and output a narrow pulse when the outputs OUT and OUT_B transition from a high state to a low state. These pulses are used to set and reset a flip-flop . The flip flop provides an output that is only dependent on the very fast fall times of the outputs OUT and OUT_B. This allows the level shifter to be designed for optimal transitional performance without the sacrifice of a potentially long propagation delay on the output nodes.

Technique for improving propagation delay of low voltage to high voltage level shifters

A distributed power device ( ) including a plurality of tank regions ( ) separated from one another by a deep n-type region ( ), and having formed in each tank region a plurality of transistors ( ). The plurality of transistors ( ) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D ) is defined from each tank region to a buried layer, and a second parasitic diode (D ) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer ( ) formed under the tank regions. The distributed parasitic diodes and resistance of the NBL layer advantageously provides that the parasitic diode (D ) between the NBL layer and the substrate will never be forward biased. In addition, each of the tank regions has a heavily doped p-type region ( ) reducing the minority carrier lifetime to provide increased switching speed of the large power FET.

Distributed power device with dual function minority carrier reduction

Method of fabricating integrated system on a chip protection circuit

An apparatus for presenting a regulated output at an output locus established at a precharge level includes: (a) an error indicator generating an error signal indicating difference between a reference signal and a sensed signal; (b) a pulse indicator coupled with the error indicator generating a pulse signal indicating difference between the error signal and a periodic signal; (c) a switching device responding to the pulse signal effecting coupling of the output locus with a first terminal or a second terminal depending upon whether the pulse signal is at a first level or a second level; and (d) a driver controller coupled with the pulse indicator and the switching device that provides a control signal to the switching device indicating at least one characteristic of the pulse signal. The switching device is operative or inoperative depending upon whether the control signal is in a first state or a second state.

Apparatus and method for controlling startup of a precharged switching regulator

Method of minimizing package-shift effects in integrated circuits by using a thick metallic overcoat

A high voltage DENMOS transistor (10) having improved ESD protection. The transistor (10) is optimized to provide maximum substrate current in order to turn on the inherent lateral npn transistor during an ESD event so that the lateral npn can dissipate the ESD event without damage to the transistor (10). This is accomplished by optimizing the overlap (A) of the drain extended region (16) and the gate electrode (28) to control the gate coupling to achieve maximum substrate current.

Efficient NPN turn-on in a high voltage DENMOS transistor for ESD

The invention is a multiplex circuit for outputing two or more signals of different levels to a common output pad where a first output driver (D.sub.h) is powered from a voltage rail having a higher voltage than at least one second output driver (D.sub.1) power by a lower voltage rail. An interface circuit (IFC) and level shift circuit provides two output signals base on a single input signal, one signal being equivalent to the voltage of the higher voltage (V.sub.High) and the other being based on the lower voltage (V.sub.low). PMOS device connected to the output pad has its back gate connected to V.sub.high to prevent leakage current through the PMOS device when the output to the output pad (P.sub.1) is equivalent to V.sub.High.

Multiplexing a single output node with multiple output circuits with

Method of making an efficient NPN turn-on in a high voltage DENMOS

A LDMOS having improved ESD reliability and a method for designing such a LDMOS. A higher gate clamp voltage and/or minimized drain clamp voltage is used to maximize the ESD performance of the LDMOS. Given a set of design parameters, one or more of the gate clamp voltage, drain clamp voltage, or size of the LDMOS are optimized to meet the design parameters while achieving the optimum ESD performance.

Lateral DMOS design for ESD protection

A signal driver circuit (10) is provided that comprises a first inverter comprising a P-FET (14), an N-FET (16) and a resistor (18). A second inverter comprises a P-FET (20) and an N-FET (22). Resistor (18) and capacitors (24) and (26) limit the transition times of the output driving signal to control electromagnetic radiation caused by rapid transition times in the output signal. Circuit (10) is independent of the amount of capacitive load (28) driven by the circuit.

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Richardson, TX, United States of America

David D Briggs