Agilent Technologies, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies General IP Pte, Ltd.

David D Balhiser

Jason Todd Gentry

Gayvin E Stong

Bryan Haskin

Ronald G Harber

Paul J Marcoux

Under control of an input signal, a signal line is driven toward a first voltage by coupling a first current path to the signal line. While the first current path is coupled to the signal line, 1) a charge boost is provided to the signal line to increase the rate at which a voltage on the signal line switches toward the first voltage, and 2) current flow through the signal line is clamped to prevent a voltage on the signal line from reaching the first voltage. The current flow may be clamped by means of a resistor in the first current path, and the charge boost may be provided by a capacitor that is coupled in parallel with the resistor.

Driver-side current clamping with non-persistent charge boost

In one disclosed method, a dynamic signal is driven onto a driven end of a first signal line, and an ungrounded bias signal is driven onto a driven end of a second signal line. The ungrounded bias signal is then received at a receiving end of the second signal line, and the dynamic signal is received at a receiving end of the first signal line. The receiving end of the second signal line is coupled to a first input of a quasi-differential receiver, and the receiving end of the first signal line is coupled to a second input of the receiver. The ungrounded bias signal is used to bias a toggle point of the receiver, and the dynamic signal is used to toggle an output of the receiver. Variations of this method, and apparatus that can perform this and other methods, are also disclosed.

Propagation of a dynamic signal to a quasi-differential receiver biased by an ungrounded driver-side bias signal

A method and system of identifying one or more nets in a digital IC design that are at risk of electromigration comprises selecting a manufacturing process for the digital IC design and obtaining a clock period and process voltage. A voltage waveform transition time and effective capacitance is calculated for one or more of the nets. A maximum allowable effective capacitance for each one of the nets is calculated based upon a peak current analysis or an RMS current analysis. The effective capacitance for each net is compared against the maximum allowable capacitance to identify those nets that are at risk of failure due to the effects of electromigration.

Process and system for identifying wires at risk of electromigration

A method and apparatus for accelerating the transmission of signals across an interconnect wire of an integrated circuit is presented. According to the method, a minimum charge level is maintained on the wire when it is driven to a low voltage level and a maximum charge level is maintained on the wire when it is driven to a high voltage level. In accordance with the apparatus of the invention, the minimum and maximum charge levels are maintained on the wire using a pair of clamping circuits which clamp the voltage level on the receiving end of the wire to a respective minimum voltage level and maximum voltage level. Accordingly, when the interconnect wire is driven to a high voltage level at a driven end of the wire, the charge level on the receiving end of the wire is already at a minimum level, resulting in less delay time to charge the wire to a high voltage level. Conversely, when the interconnect wire is driven to a low voltage level at the driven end of the wire, the charge level on the receiving end of the wire is already capped to a maximum level, which results in less delay time to drain the wire to a low voltage level.

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Fort Collins, CO, United States of America

David D Balhiser