St-ericsson Sa

Robert Boschgmbh

Stmicroelectronics (rousset) Sas

Stmicroelectronics (grenoble 2) Sas

David Coupe

Eric Bernasconi

Ludovic Chotard

Pierre-François Pugibet

Danilo Piergentili

Christophe Eychenne

Giuseppe Montalbano

Gilles Spinelli

A clock fractional divider module which is formed as, comprises or has integrated therein a dual-core lock step unit. The dual-core lock step unit is configured in order to realize a clock fractional division arrangement, mechanism or process accompanied by an error detection, recognition and/or correction arrangement, mechanism or process.

Clock fractional divider module, image and/or video processing module, and apparatus

An electronic device can be used for synchronizing tasks of an appliance that includes a memory access controller having inputs associated with priority levels. The device includes control circuits configured for receiving signals from events and delivering in response signals for activation of tasks. A configurable interface for external events designed to receive first event signals from at least one circuit of the appliance and to route some of them to the corresponding control circuits as a function of a first law of correspondence. A configurable interface for internal events designed to receive second event signals corresponding to the signals for activation of tasks and to route some of them to the control circuits as a function of a second law of correspondence.

Electronic device for synchronizing tasks of an electronic appliance

A process and circuit for blending a foreground image (B) with a background image (A), said foreground and background images being arranged in pixels and having color representations (R, G, B). The foreground foreground image (A) has a transparency parameter (T(x,y)) in accordance with a so-called alpha plane representative of the transparency profile to apply to the foreground image. The process involves the steps of: -applying a dithering method on said alpha plane in order to convert said transparency parameter (T) into a one-bit transparency parameter (T'); -use said one-bit transparency parameter (T&#x2032;) for controlling a multiplexing unit having two inputs respectively receiving the foreground image (A) and the background image (B). In one embodiment, the one-bit transparency parameter T&#x2032; into the two extreme values of a range of continuous values, for instance coded on 8 bits. The process then applies a four-pixel interpolation method to the foreground image (A) for the purpose of creating a five level transparency parameter in the blending process, and then uses the five level transparency parameter for controlling a multiplexing circuit for the purpose of achieving blending of the foreground image with the background image.

Process and apparatus for blending images

Memory management process for optimizing the access to a central memory located within a processing system comprising a set of specific units communicating with each other through said memory, said process involving the steps of: a) arranging in a local memory at least a first and a second bank of storage (A, B) for the purpose of temporary object exchanged between a first data object producer () and a second data object consumer (); b) arranging a address translation process for mapping the real address of an object to be stored within said banks into the address of the bank; b) receiving one object produced by said producer and dividing it into stripes of reduced size; c) storing the first stripe into said first bank; d) storing the next stripe into said second bank while the preceding stripe is read by said object consumer (); e) storing the next stripe into said first bank again while the preceding stripe is read by said object consumer (). f) repeating e) and c) until all stripes composing said data objects have been processed; g) arranging an interlocking mechanism for locking the writing and reading process in said banks to ensure producer has enough space to forward further data, as well as receiver has indeed data to read.

Memory management process and apparatus for the same

Growing community of inventors

Valbonne, France

David Coupe