Microsemi Semiconductor Ulc

Microsemi Semiconductor (u.s.) Inc.

David Colby

Tanmay Zargar

Krste Mitric

Paul H L M Schram

Slobodan Milijevic

Dean Morgan

Cathy Zhang

Siddharth Raghunandan

Joep De Rijk

Paul Schram

Robertus Van Der Valk

An acoustic delay measurement apparatus measures an audio delay introduced by an audio system. A programmable delay buffer, which introduces a programmable delay into the audio stream, receives an audio stream from an audio source and outputs a reference signal representing the audio stream. An adaptive filter is responsive to the reference signal to generate an estimate signal to match on convergence of the adaptive filter an audio signal output by the audio system, which is the audio stream delayed by an amount representative of the audio delay introduced by the audio system. A processor including a coefficient analysis block reads coefficients in the adaptive filter after convergence, computes a delay introduced into said estimate signal by the adaptive filter, and adds the computed delay to the programmable delay buffer to provide a measurement of the audio delay.

Acoustic delay measurement using adaptive filter with programmable delay buffer

A clock generator with glitchless phase adjustment having a phase locked loop with a controlled oscillator providing an output representing a phase value. One or more output modules generate one or more output clocks from the output. One or more adjustment modules add a requested phase adjustment to an output clock. The phase adjustment modules are configured to break the requested phase adjustment into smaller increments and apply the increments to an output clock generated in said at the output modules one cycle at a time.

PLL glitchless phase adjustment system

A digital phase locked loop has a phase acquisition module that outputs a first phase value representative of the phase of a reference signal expressed with respect to an internal phase reference. A phase offset write module convert a phases offset commanded from an external source into a phase offset correction value expressed with respect to the internal phase reference. A phase offset controller sums the phase offset correction values to produce a second phase value, which is added to the first phase value to produce a third phase value expressed with respect to the internal phase reference. A digital controlled oscillator (DCO) outputs a fourth phase value expressed with respect to the internal phase reference. A phase detector outputs a fifth phase value representing the difference between the third and fourth phase values. A loop filter derives a frequency offset for the DCO based on the fifth phase value. An output module generates one or more output clocks from the fourth phase value.

Phase locked loop with the ability to accurately apply phase offset corrections while maintaining the loop filter characteristics

A phase-locked loop to is simultaneously synchronized to high and low frequency clocks by (i) locking an output of the phase-locked loop to a high-frequency reference clock, (ii) measuring at a high rate a first phase difference between the high-frequency reference clock and the output of the phase-locked loop, (iii) measuring at a high rate a second phase difference between a low-frequency reference clock and the output of the phase-locked loop; (iv) computing at a low rate from said first and second phase differences a third phase difference between the high-frequency and low frequency clocks; (v) combining at a low rate said third phase difference with said second phase-difference to obtain a total phase difference; and (vi) adjusting the output of the phase-locked loop at a low rate to reduce the obtained total phase difference.

Phase locked loop with simultaneous locking to low and high frequency clocks

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Austin, TX, United States of America

David Colby