Motorola Corporation

Freescale Semiconductor,inc.

Nxp Usa, Inc.

David Clegg

Tingdong Zhou

Tu-Anh N Tran

Stuart E Greer

Sohrab Safai

Suresh Venkatesan

Olubunmi O Adetutu

Douglas Michael Reber

Alexander Barr

Trent Uehling

Robert Joseph Wenzel

James S Golab

Ramnath Venkatraman

Brian George Anthony

Terry E Burnette

Gregor Braeckelmann

Stephen R Crown

Rebecca G Cole

Embodiments of a semiconductor packaged device and method of making thereof are provided, the device including a substrate; a first flip chip die mounted to a first major surface of the substrate; a second flip chip die mounted to the first major surface of the substrate, the second flip chip die laterally adjacent to the first flip chip die on the first major surface; and a wire bond formed between a first bond pad on the first flip chip die and a second bond pad on the second flip chip die.

Multiple interconnections between die

Embodiments of an interconnect structure are provided, the interconnect structure including: a reference plane structure having a first major surface and a second major surface opposite the first major surface, the reference plane structure including a plurality of through holes from the first major surface to the second major surface; a plurality of conductive columns, each conductive column centered within a through hole; and a plurality of isolation structures, each isolation structure fills an annular region within the through hole between each conductive column and surrounding portion of the reference plane structure.

Package to board interconnect structure with built-in reference plane structure

A conductive structure is formed in a last metal layer of an integrated circuit. Passivation material is patterned over a portion of the conductive structure. A first trench is patterned around a selected portion of the passivation material. The selected portion represents a bond region of a wire bond to be formed above the passivation material. A portion of the passivation material completely covers a bottom of the trench. A layer of conductive material is conformally deposited over the passivation material. The conformal depositing resulting in a second trench forming in the conductive material over the first trench in the passivation material. The second trench is positioned to contain at least a portion of a splash of the conductive material when the wire bond is subsequently formed.

Bond pad having a trench and method for forming

A semiconductor device comprises an integrated circuit including a wire bond pad and a passivation material, and a first gap between a first selected portion of the wire bond pad and the passivation material. The first gap is positioned to contain at least a first portion of a splash of the wire bond pad formed during a wire bond process.

Bond pad and passivation layer having a gap and method for forming

An interconnect overlies a semiconductor device substrate ( ). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer ( ) overlies the conductive barrier layer and the passivation layer ( ) has an opening that exposes portions of the conductive barrier layer ( ). In an alternate embodiment a passivation layer ( ) overlies the interconnect, the passivation layer ( ) has an opening ( ) that exposes the interconnect and a conductive barrier layer ( ) overlies the interconnect within the opening ( ).

Method of forming semiconductor device including interconnect barrier layers

Multiplexed joining of solder bumps to various substrates for assembly of an integrated circuit package includes placing a semiconductor substrate (312) having solder bump structures (314) in contact with a ceramic substrate (320 having chip pads (322, 334), and placing this structure in contact with ball grid array spheres (352) in order to form a CBGA (360) in a single flow process. The method includes the steps of providing a semiconductor device having at least one first interconnect structure connected to a surface of the semiconductor device (501), and a substrate having a plurality of metallized pads (503); placing an at least one second interconnect structure in aligned contact with one or more of the plurality of metallized pads (505); placing the at least one first interconnect structure in aligned contact with one or more of the plurality of metallized pads (507); and simultaneously reflowing the at least one first interconnect structure and the at least one second interconnect structure such that the semiconductor device and at least one second interconnect structure are connected to the metallized pads of the substrate (509).

Method for multiplexed joining of solder bumps to various substrates

Growing community of inventors

Austin, TX, United States of America

David Clegg