Broadcom Corporation

David Chung

Afshin Momtaz

Xin Wang

Jun Cao

Armond Hairapetian

Mario Caresosa

Thomas J Kolze

Bruce Joseph Currivan

Namik Kocaman

Guangming Yin

Ichiro Fujimori

Davide Tonietto

Kang Xiao

Jay Proano

Vikram Natarajan

Randy Stolaruk

Natarajan Vikram

Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.

High speed receive equalizer architecture

Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.

Transceiver system and method supporting variable rates and multiple protocols

Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

Methods and circuitry for implementing first-in first-out structure

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Irvine, CA, United States of America

David Chung