International Business Machines Corporation

David Christopher Kuchinski

Eric Eugene Retter

James Warren Dieffenderfer

David B Rolfe

Michael C Dapp

Billy J Knowles

Vincent John Smoral

Clive Allan Collins

Richard Edward Nier

Robert Reist Richardson

Peter Michael Kogge

Paul Amba Wilkinson

Thomas Norman Barker

Nicholas Jerome Schoonover

Donald Michael Lesmeister

Richard Ernest Miles

James Robert Stupp

Donald George Grice

Donald G Grice

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processor memory elements on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. The architecture uses all the pins for networking. Each chip has eight 16 bit processors, and eight respective 32K memories. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. The scalable chip has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. A fully distributed programmable router is provided by the processing memory elements that form a node. There is program compatibility for the fully scalable system.

APAP I/O programmable router

A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

Advanced parallel array processor (APAP)

Advanced parallel array processor(APAP)

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Owego, NY, United States of America

David Christopher Kuchinski