Fairchild Semiconductor Corporation

David Chong

Hun Kwang Lee

Lay Yeap Lim

Rajeev Dinkar Joshi

Chung-Lin Wu

Oseob Jeon

Maria Cristina B Estacio

Venkat Iyer

Boon Huan Gooi

Yoonhwa Choi

Byoung-Ok Lee

Tan Teik Keng

Shibaek Nam

Howard Allen

Stephen Martin

Jatinder Kumar

Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Semiconductor die package and method for making the same

In one implementation, an apparatus includes a semiconductor die, a lead, a non-conductive epoxy, and a conductive epoxy. The semiconductor die includes an upper surface and a lower surface opposite the upper surface. The lead is electrically coupled to the upper surface of the semiconductor die. The non-conductive epoxy is disposed on a first portion of the lower surface of the semiconductor die. The conductive epoxy is disposed on a second portion of the lower surface of the semiconductor die. In some implementations, a conductive wire extends from the lead to the upper surface of the semiconductor die to electrically couple the lead to the upper surface of the semiconductor die.

Conductive chip disposed on lead semiconductor package

A lead frame with patterned conductive runs on the top surface to accept a wire bonded or flip-chip or COL configuration is disclosed. The top pattern is completed and the bottom is etched away creating cavities. The cavities are filled with a pre-mold material that lend structural support of the lead frame. The top is then etch through the lead frame to the pre-mold, except with the top conductive runs exist. In this manner the conductive runs are completed and isolated from each other so that the placement of the runs is flexible. The chips are mounted and the encapsulated and the lead frames are singulated. The pattern on the top and the bottom may be defined by first plated the patterns desired.

Method of making and designing lead frames for semiconductor packages

A package system for integrated circuit (IC) chips and a method for making such a package system. The method uses a solder-ball flip-chip method for connecting the IC chips onto a lead frame that has pre-formed gull-wing leads only on the source/gate side of the chip. A boschman molding technique is used for the encapsulation process, leaving exposed land and die bottoms for a direct connection to a circuit board. The resulting packaged IC chip has the source of the chip directly connected to the lead frame by solder balls. As well, the drain and gate of the chip are directly mounted to the circuit board without the need for leads from the drain side of the chip.

Packaging system for semiconductor devices

A die attach package for connecting a die or chip of die-down orientation to a printed circuit board in a die-up orientation. The package includes a substrate with leads that may be traces terminating in vias or that may be the leads of a lead frame. The traces or the leads of the lead frame are modified such that they pass under the die when the die is attached. The traces or leads are routed under the die such that proper connections are established from the topside of the die to the appropriate mount locations of the printed circuit board. The die is attached to the substrate using a non-electrically-conductive material. This packaging enables a fabricator to make die of one orientation type, die down, and use that die in a die-up package, thereby saving on fabrication costs.

Packaging system for die-up connection of a die-down oriented integrated circuit

Growing community of inventors

Penang, Malaysia

David Chong