National Semiconductor Corporation

Texas Instruments Corporation

David Chin

Jaime A Bayan

Nghia Thuc Tu

Will Kiang Wong

Anindya Poddar

Mohammad Waseem Hussain

Artur Darbinyan

Dorothy Lyou Mantle

Kurt E Sincerbox

A semiconductor device package includes a leadless leadframe, and a plurality of terminal pads extending to a periphery of the leadframe. At least two of the plurality of terminal pads are interior extending terminal pads that include an interior portion having a shape including at least one curved portion and an exterior portion that extends to the periphery of the leadframe. An integrated circuit (IC) die having at least a semiconductor surface includes circuitry configured for at least one function having nodes connected to bond pads on the leadframe. There is a bonding arrangement between the plurality of terminal pads and the bond pads. A mold compound is for encapsulation of the semiconductor device package.

Leadless leadframe and semiconductor device package therefrom

An apparatus for incorporating a metallic foil into a semiconductor package includes a carrier embossed with a multiplicity of cavities. Each of the cavities define a pedestal recessed with the cavities which penetrate only partially through the thickness of the carrier. A metallic foil overlying a pattern with the pedestals in direct contact and help support the metallic foil with the metallic foil pressed into at least some of the cavities. In other embodiments, a gap is between the metallic foil and bottoms of the cavities in a substrate. Integrated circuit dice are attached to the foil. Each die is attached to the foil in a region of the foil overlying a portion of the at least one device area pattern. Bonding wires electrically connect the integrated circuit dice to the foil.

Thin foil semiconductor package

A method of fabricating chip carriers suitable for use in packaging integrated circuits and other electronic, electro-mechanical and opto-electronic devices is described. In general, a number of wires (or wires and rods) are arranged in parallel in a wiring fixture. After the wires are positioned, they are encapsulated to form an encapsulated wiring block. The wiring block is then sliced to form a number of discrete panels. Preferably, the various wires are geometrically positioned such that each resulting panel has a large number of device areas defined therein. The encapsulant in each panel effectively forms a substrate and the wire segments in each panel form conductive vias that extend through the substrate. The resulting panels/chip carriers can then be used in a wide variety of packaging applications.

Universal chip carrier and method

The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. In one embodiment, a foil carrier structure is formed by ultrasonically bonding portions of a conductive foil to a metallic carrier. The bonded portions define panels in the foil carrier structure. In some embodiments, the foil carrier structure is cut to form multiple isolated panels that are sealed along their peripheries. Each isolated panel may be approximately the size of a conventional leadframe strip or panel. As a result, existing packaging equipment may be used to add dice, bonding wires and molding material to the panel. The ultrasonic welding helps prevent unwanted substances from penetrating the foil carrier structure during such processing steps. After the carrier portion of the molded foil carrier structure is removed, the structure is singulated into integrated circuit packages. Some embodiments relate to methods that utilize some or all of the aforementioned operations. Other embodiments relate to arrangements used in the above processes.

Method of making foil based semiconductor package

The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages.

The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One embodiment of the present invention involves attaching multiple dice to a foil carrier structure. The foil carrier structure is made of a thin foil that is bonded to a carrier. The dice and at least a portion of the metallic foil is then encapsulated with a molding material. The carrier is removed, leaving behind a molded foil structure. The exposed foil is patterned and etched using photolithographic techniques to define multiple device areas in the foil. Each device area includes multiple conductive lines. Afterwards, portions of the conductive lines are covered with a dielectric material and other portions are left exposed to define multiple bond pads in the device area. The molded foil structure can be singulated to form multiple integrated circuit packages.

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Cupertino, CA, United States of America

David Chin