Ati International Srl

Ati Technologies Inc.

David Chih

Erwin Pang

Syed Athar Hussain

Vladimir F Giemborek

Lee K Lau

Wai-Leong Poon

Charles Y W Leung

Chen-Jen Jerry Chang

Keith S K Lee

David Y K Ho

Minghua Zhu

A method and apparatus matches one or more clock speeds used in, or used by, a graphics accelerator so as to match graphics processing requirements to the speed of the clock source or sources. Clock speed is adjusted under software control to match current requirements. Power is conserved by reducing clock speeds from unnecessarily high rates to a rate that can satisfy current display mode settings and other graphics processing demands.

Power consumption management in a video graphics accelerator

A circuit and method serves as a slave interface to support both register read/write and monitor detection operations by a graphics controller chip, or other display data source, with a plurality of display devices. The circuit supports differing monitor detection protocols including, for example, IC protocol and non-DDC type protocols. The circuit may be set in two modes, a register mode and a bypass mode. The register mode is used to facilitate standard IC protocol to a display device. Display detection bypass circuitry is used to selectively bypass the register based display detector interface by connecting input pins to any two of a plurality of I/O pins so that the system may be used for monitor detection of a plurality of different display devices, such as CRTs and LCDs to facilitate multiprotocol display detection.

Serial communication circuit with display detector interface bypass circuit

A FIFO memory device, FIFO control method and graphics processing system are disclosed which incorporate spread-spectrum EMI compensation. In one embodiment, a FIFO memory device and method includes generating a spread-spectrum adjustment signal for a spread-spectrum FIFO based on an address offset associated with a read and write address associated with a spread-spectrum FIFO. The method includes adjusting the spread-spectrum clock signal in response to the spread-spectrum adjustment signal based on the address offset associated with the read and write address. A spread-spectrum FIFO receives data from a data source, such as a graphics data source, which may include a memory such as a RAMDAC. The data can be provided by a display engine or other suitable information provider. The spread-spectrum FIFO is operatively responsive to both a spread-spectrum clock signal and another clock signal to suitably adjust an output frequency of data read from the spread-spectrum FIFO using fewer than two complete display paths and associated circuitry and operations.

Spread spectrum FIFO and method for storing data for multiple display types

An integrated circuit for graphics processing that includes a configurable display interface includes video graphics circuitry, a data encoder, transmission circuitry and configuration registers. The video graphics circuitry produces video data that is formatted to drive a display. The data encoder is operably coupled to the video graphics circuitry and encodes the digital video data to produce transmission data. The transmission data is then provided to the transmission circuitry operably coupled to the data encoder. The transmission circuitry combines the transmission data with control information that is retrieved from registers included in the integrated circuit. The transmission circuitry transmits the transmission data over a plurality of differential signals, where the swing amplitude of the differential signals is configured using additional registers included in the integrated circuit.

Integrated circuit for graphics processing including configurable display interface and method therefore

A method and apparatus for a multi-chip module that is testable and reconfigurable based on testing results is accomplished by a multi-chip module that includes a first circuit disposed on a first chip substrate, a second circuit disposed on second chip substrate, and an interconnecting substrate operably coupled to the first chip substrate and the second chip substrate. The interconnecting substrate connects the first circuit to the second circuit. The interconnecting substrate includes external connectors for accessing signals within the multi-chip module, which allow the multi-chip module to be fully tested. This testing may include isolating the first circuit and/or the second circuit by disabling other circuits in order to allow each of the circuits to be exercised without interference from other circuits. After testing the multi-chip module, configuration circuitry included on the multi-chip module may be used to reconfigure the multi-chip module based on results of the testing.

Method and apparatus for a multi-chip module that is testable and reconfigurable based on testing results

A memory allocator employs a programmable and controllable switching circuit which switches multiple address buses and multiple data buses connected to the digital signal processing unit to differing banks of memory depending upon determined system requirement data, such as the amount of program memory and data memory necessary for a particular application. The memory space may be separate banks of memory incorporated into pools of memory if desired. The controllable switching circuit multiplexes the appropriate address bus and data bus to a given memory block or blocks which may be independent and can still be dedicated to specific application tasks. The memory banks are normal single address port and single data-port banks but are allowed to be connected to multiple data buses and address buses through the switching circuit. The switching circuit is sized to allow access to a subset of banks in a pool of banks associated with a given memory port. The digital signal processor is a multi-port device.

Switchable memory system and memory allocation method

A display data format conversion circuit and method facilitates display of data on a plurality of display devices based on display data of a source display device. The system incorporates a resynchronization circuit that dynamically varies a frame rate of one display device based on the instantaneous frame rate of the source device to maintain synchronization of the displays. A display timing generator circuit for a first display, such as an LCD display, produces a first display timing signal. The resynchronization circuit is operatively responsive to the first display timing signal and a second display timing signal wherein the second display timing signal is associated with a second display device, such as a source display device. In one embodiment, the resynchronization circuit includes a vertical blanking time variation circuit that adaptively and continuously varies the frame rate of the first display device by varying a vertical blanking time of the first display device.

Growing community of inventors

Scarborough, Canada

David Chih