Western Digital Technologies, Inc.

National Semiconductor Corporation

Sandisk Technologies Inc.

Marvell Israel (misl) Ltd.

David Chaim Brief

Yoav Markus

Yuval Grossman

Rotem Sela

Gregory Lewis Dean

Paul A Lassa

Refael Ben-Rubi

Arseniy Aharonov

Asaf Gueta

Amir Rozen

Kent Bruce Waterson

Ohad Falik

Shlomo Naidorf

Lee M Gavens

Opher Lieber

Neil David Hutchison

David James Fensore

Eran Arad

Tomer Spector

Shemmer Choresh

Moshe Cohen

Uri Shir

Sebastien Andre Jean

Mikhael Zaidman

Nagdi Tafish

Ahiad Turgeman

Shai Levi

Data may be read from a data storage device using host performance booster (HPB). An encoded HPB entry in a read command provides the PBA (Physical Block Address) as well as the run length. The LBA (Logical Block Address), PBA, and run length are placed in an HPB read buffer table. The HPB read buffer table is located in the host device. When the read command is received by the data storage device, the data storage device reads the LBA, transfer length, and HPB entry from the read command. The HPB entry contains the PBA for the LBA as well as the run length for the data to be read. For non-sequential reads, the HPB contains the LBA, transfer length, and reference to a write buffer table that is stored in the data storage device.

Boosting reads of chunks of data

A method and apparatus for dynamically monitoring, measuring, and adjusting a clock duty cycle of an operating storage device is disclosed. A storage device includes a measuring circuit comprising a plurality of flip flop registers coupled to a first input line, with each flip flop register having a first input and a second input. One or more delay taps are coupled to each flip flop register, and are disposed on a second input line. While the device operates, a clock signal is input directly into the first input of each flip flop register via the first input line. Simultaneously, the clock signal is input into the second input of each flip flop register through the one or more delay taps via the second input line. The flip flop registers are then read to determine the clock duty cycle of the device, and the clock frequency is adjusted as needed.

Measurement, calibration and tuning of memory bus duty cycle

A method of searching a database that includes executing a trie search algorithm on a first portion of data in the database, returning a tag narrowing a location of the first portion of data to optimize the database, and performing a directed search of the optimized database by executing the trie search algorithm again on the optimized database, where the trie search algorithm is an information retrieval data structure using a M-ary tree where each node consists of a M-positional vector of pointers.

Trie search engine

Disclosed are systems and methods for providing an improved hardware-assisted multi-table database with reduced memory footprint. A method includes receiving a request to perform an operation on a selected logical table of a plurality of logical database tables. The method also includes accessing a data structure comprising a plurality of records each including: a logical table identifier corresponding to one of the plurality of logical database tables, wherein the logical table identifier is accessed from a register, and at least one sort key. The method also includes performing the operation using one or more sort criteria, wherein the one or more sort criteria are maintained for the selected logical table using the at least one sort key of the plurality of records corresponding to the selected logical table. The method also includes updating the data structure to reflect the performed operation.

Hardware-assisted multi-table database with shared memory footprint

An arrangement is illustrated wherein a flash controller with a multi-constraints dynamic resource manager module configured to control both software and hardware clients is provided. The arrangement also provides for memory and an interface for connecting the controller to a host.

Multi-constraint dynamic resource manager

A method of sending a command from a slave storage device to a master host includes receiving an initial command from the master host. A callback response containing a requested command triggered by the initial command is sent by the slave storage device. In one embodiment, the master host is a Universal Flash Storage (UFS) host and the slave storage device is a UFS storage device. In one embodiment, the initial command is a start stop unit (SSU) command with a power condition field of sleep or powerdown and the requested command is a read buffer command. In another embodiment, the initial command is a start stop unit (SSU) command with a power condition field of active and the requested command is a write buffer command.

Storage device with a callback response

A system and method for time stamp synchronization are disclosed. In one embodiment, first and second devices are provided. The second device receives a first time stamp of the first device, wherein the first time stamp was generated in response to a time stamp synchronization event common to the first and second devices; generates a second time stamp of the second device in response to the time stamp synchronization event, wherein the first and second time stamps are in different time domains; and correlates the first and second time stamps, wherein correlating the first and second time stamps provide a relationship between the time domains because the first and second time stamps were both generated with respect to the same time stamp synchronization event common to the first and second devices.

System and method for time stamp synchronization

An apparatus includes an inversion circuit configured to invert a data word, a first partial-inversion circuit configured to invert a first portion of the data word, a second partial-inversion circuit configured to invert a second portion of the data word, and an output selection circuit configured to compare: the data word, an output of the inversion circuit, an output of the first partial-inversion circuit, and an output of the second partial-inversion circuit with a prior data word, and to select an output according to respective numbers of changed bits from the prior data word.

Non-volatile storage device with adaptive data bus inversion

An apparatus includes one or more processors configured to execute instructions to generate a plurality of event results that includes a first event result and a second event result. The apparatus further includes a first buffer coupled to the one or more processors and a second buffer coupled to the first buffer. The first buffer is configured to store the plurality of event results. The apparatus further includes a circuit coupled to the first buffer. The first buffer is further configured to provide the first event result to the second buffer in response to detection by the circuit of a failure condition associated with the first event result.

Selective event logging

An apparatus includes an event message generator configured to generate an event message. The apparatus further includes a filter circuit configured to receive the event message and to send a first portion of the event message to a destination device. The filter circuit is further configured to selectively send a second portion of the event message to the destination device at least partially based on an event traffic load associated with the destination device.

Selective event filtering

A system on a chip or storage device has a dynamic process for handling system events that are transmitted at varying transmission rates. This dynamic process is a hybrid mode of operation that tailors the use of time stamp information according to the dynamic flow of events that are submitted in the system. Relative time stamps can be used along with explicit time stamps. Periodic wrap around events which use relative time stamps based on the periodic wrap events may be suppressed when there were no events between consecutive wrap around events. When an asynchronous event occurs during the suppression, the event is identified with a high precision time stamp (HPTS) rather than a relative time stamp. The periodic wrap around events can be re-initiated after the HPTS event is stamped.

Timestamp suppression

Apparatuses and methods implemented therein are disclosed for generating event codes that include the source of the events that caused the generation of the event codes. In one embodiment the apparatus comprises a memory, a processor, logic element and an event generator. The memory is configured to store instructions corresponding to a scheduler and instructions corresponding to a first thread and a second thread. The processor is configured to execute instructions corresponding to the scheduler wherein the scheduler selects a one of the first or second thread wherein the processor executes instructions corresponding to the selected one of the first or second thread. The logic element is configured to receive an identifier corresponding to the selected thread and a received asynchronous event. The logic element produces a concatenated event identifier comprising the thread identifier and the received asynchronous event.

Apparatuses and methods for generating event codes including event source

Systems, methods, and apparatuses are provided to obtain diagnostic information from a storage device. A read command may be transmitted to a storage device, where the read command conforms to a block level storage protocol and is directed to an unused logical unit of storage memory included in the storage device, to an invalid logical block address, and/or to a mode page. The unused logical unit may be a predetermined logical unit of the storage memory that is not allocated by a file system. Diagnostic data may be received from the storage device in response to the read command. The diagnostic data may be information related to operation of the storage device and/or a component of the storage device.

Growing community of inventors

Modiin, Israel

David Chaim Brief