Maxim Integrated Products, Inc.

David Castaneda

Chowdhury F Rahim

Gary G Fang

Yuanfang Li

Daniel David Alexander

Patrick Yin Chan

Jean CauXuan Le

Rahim F Chowdhury

Ling Liu

Bo Yang

Huibo Liu

A system includes a sub-binary radix digital-to-analog converter (DAC) that converts a digital input signal to an analog output signal based on a sub-radix DAC code. A radix conversion module performs radix conversion on the digital input signal. To perform the radix conversion, the radix conversion module associates bit positions corresponding to the digital input signal with respective analog weights and converts the digital input signal to the sub-radix DAC code based on the respective analog weights.

Precision sub-RADIX2 DAC with analog weight based calibration

An N bit sub-binary radix digital-to analog converter (DAC) includes a radix conversion module that converts an m bit digital input signal to an N bit sub-radix DAC code. A ladder module having NL bits has a plurality of first circuit elements corresponding to first respective bits of the N bit sub-radix DAC code. A segment module having NS bits has at least one second circuit element corresponding to second respective bits of the N bit sub-radix DAC code. N&#x3e;m, and N is the sum of NL and NS.

[object Object]

A system includes an NL bit digital to analog converter (DAC) ladder module having NL ladder resistors connected in parallel, NL series resistors connected in series between the NL ladder resistors, and a plurality of switches. NL is an integer greater than one. Adjacent pairs of the plurality of switches are connected in series with respective ones of the ladder resistors. On resistances of each of the plurality of switches are approximately equal. A switch control module provides a plurality of switch control signals to respective ones of the plurality of switches.

DAC with novel switch regulation

A driver circuit uses a feedback loop having a programmable timer and timer logic to adjust a slew rate delay period used to accommodate slewing current when charging or discharging a load capacitor, and to increase the current limit during the slew rate delay period by selecting a larger input current reference value. Increasing the current limit provides for a faster settling time. The value of each input current reference value can be programmed. The programmable timer and the timer logic can be configured to coordinate the slew rate delay period and the selected input current reference value. The slew rate delay period can be adjusted based on which input current reference value is applied.

Timer controlled, short and open circuit fault detection with slew-rate boosted output driver

A system includes an N bit sub-binary radix digital-to-analog converter (DAC) that converts an m bit digital input signal to an analog output signal, where m and N are integers greater than or equal to 1 and N&#x3e;m. A radix conversion module determines a code ratio, the code ratio being a ratio of a total number of available monotonic codes to 2, and performs radix conversion on the m bit digital input signal based on the code ratio.

Digital to analog converters having a hybrid two-stage structure. The first stage is a differential segmented current DAC controlled by the MSBs (most significant bits) of input data. The second stage is a resistor string DAC controlled by the LSBs (least significant bits) of the input data to interpolate between the differential outputs of the first stage. The resistor string is directly connected to the current DAC without the need of buffer amplifiers. Instead, a replica circuit is used to prevent the second-stage resistor string from loading the first stage current DAC. Compensation techniques are described.

Replica compensated heterogeneous DACs and methods

Operating range of R-2R ladders for digital to analog converters (DACs) is improved by increasing resistance in series with a termination switch in a termination leg to avoid transistor saturation for increasing DAC resolution, increasing reference voltage range, or other application. The switched R-2R ladder circuit is modified to compensate for increasing resistance to maintain proper resistor matching for generation of the appropriate range of analog output voltages for a digital input signal.

Method and apparatus for digital to analog converters with improved switched R-2R ladders

Asynchronous and synchronous deglitch controllers controlling switches of sample and hold circuits for deglitching digital to analog converters. Asynchronous and synchronous deglitch controllers detect transitions in the state of the digital input code to trigger or allow a one shot pulse to cause sample and hold circuits to go into hold mode for the period of the one shot pulse. Secondary glitch cancellation circuitry models the environment of the sample and hold circuit to emulate secondary glitch impulse generation. A differential amplifier substantially cancels secondary glitches related to the parasitic charges generated by the switching of the sample and hold circuit.

Method and apparatus for deglitching digital to analog converters

A varying power supply range, that can exceed the breakdown voltage of switches within a DAC, is used to generate positive and negative generated OFF voltages substantially fixed and less than the breakdown voltage to accommodate a wide range of analog reference voltages and power supply voltages. The digital input signal having digital input levels is received by a TTL/CMOS input receiver and level shifted to logic levels having the positive and negative generate voltage levels. A circuit matches switch resistance and forms positive and negative switch ON voltage levels from the voltage levels of the input positive and negative analog reference levels. Switch drivers properly drive control terminals of the switches with appropriate voltage levels avoiding switch breakdown in response to the digital input signal.

Method and apparatus for switching low voltage CMOS switches in high voltage digital to analog converters

Buffers having an output pull-up transistor controlled by the input signal, an output pull-down transistor and a pull-down transistor control circuit. A current source provides a current that is divided between the pull-up transistor and the pull-down transistor control circuit to maintain the desired output voltage. A boost capacitor is coupled between the output and the pull-down transistor control circuit to provide good dynamic response to the circuit even in the presence of substantial capacitive loads on the output. In addition a second capacitor is coupled between the pull-down transistor control circuit and a fixed voltage to provide a low frequency pole internal to the circuit. The connection of the boost capacitor to the pull-down transistor control circuit and the connection of the second capacitor to the pull-down transistor control circuit are separated by a substantial resistance, allowing the effect of each capacitor to be substantially independent of each other. Exemplary circuits are disclosed incorporating these and other features.

Growing community of inventors

Morgan Hill, CA, United States of America

David Castaneda