Altera Corporation

Databricks Inc.

David Cashman

David Lewis

Andy Louie Lee

Ketan Padalia

Michael David Hutton

Jinyong Yuan

Henry Kim

Jeffrey Christopher Chromczak

Jay Schleicher

Vaughn Betz

Paul Leventis

Tim Michael Vanderhoek

Christopher F Lane

Gregg William Baeckler

David Edward Jefferson

Valavan Manohararajah

Brian D Johnson

Hyun Mo Yi

Ketan H Zaveri

Vikram Santurkar

Giles V Powell

Alexander Behm

Triet M Nguyen

Lu Zhou

Michael Chan

Shoumik Palkar

Kimberly Anne Bozman

Jinyoung Yuan

The present application discloses a method, system, and computer system for processing data. The method includes obtaining a query plan for processing input data in response to a query, obtaining the input data, selecting a batch of the input data, creating a metadata structure for the batch, allocating one or more contiguous parts of a memory for processing the batch, processing the batch in accordance with the metadata structure to generate resulting data, and storing each array of the resulting data for the batch in one of the one or more contiguous parts of the memory.

Nested array batch processing

A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a 'K-LUT'). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT. An output line network includes a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture. The described LUT's can perform arithmetic efficiently, as well as non-arithmetic functions.

Structures for LUT-based arithmetic in PLDs

A multi-chip package may include first and second integrated circuit dies that are each partitioned into multiple logic regions. The logic regions of the first and second dies may be coupled via interconnects. Each integrated circuit die may include at least one spare logic region. Multiple logic groups may be formed with each logic group including logic regions from the first and second integrated circuit dies and the interconnects that couple those logic regions. The logic groups may be evaluated to identify defective logic groups. In response to identifying a defective logic group, the defective logic group may be repaired by configuring the first and second integrated circuit dies to stop using the defective logic group and to use a spare logic group. The spare logic group may include spare logic regions of the first and second dies that are coupled by spare logic region interconnects.

Methods and apparatus for providing redundancy on multi-chip devices

Integrated circuits with repairable logic regions are provided. Each logic region may be organized into a predetermined number of rows of logic circuitry, one of which serves as a spare row. A repairable region may be operable in normal mode or redundant mode. In normal mode, the spare row is deactivated. When one of the logic region rows contains defective circuitry, that logic region is operated in redundant mode so that each row below the bad row is shifted down by one row and the spare row is engaged to serve as the last row to repair that region. Each row may include a multiplexer and an associated driver that drives a corresponding vertical routing segment from one row to the next. Each vertical routing segment has the option of being driven by its logically equivalent vertical wire in the immediate preceding row by configuring the corresponding multiplexer.

Programmable integrated circuits with redundant circuitry

A programmable logic region on a programmable integrated circuit may include a first set of look-up tables that receive programmable logic region input signals and a second set of look-up tables that produce programmable logic region output signals. Multiplexer circuitry may be interposed between the first and second sets of look-up tables. The multiplexer circuitry may receive the programmable logic region input signals in parallel with the output signals from the first set of look-up tables and may provide corresponding selected signals to the second set of look-up tables. The programmable logic region input signals may be shared by the first and second sets of look-up tables. Logic circuitry may be coupled to outputs of the first and second sets of look-up tables. The logic circuitry may be configured to logically combine output signals from the first and second sets of look-up tables.

Integrated circuits with multi-stage logic regions

Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.

Robust time borrowing pulse latches

Systems and methods for managing a write operation are described. The systems include a logic element (LE) including an N-input look-up table (LUT) having a configurable random access memory (CRAM) including 2memory cells. The systems further include a write address decoder coupled to the LE and a write address hard logic register that stores an address of one of the memory cells. N is an integer. The hard logic register removes a dependency of a timing relationship between a write address launch and a write to the CRAM on a design of an integrated circuit.

Methods and systems for managing a write operation

Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch.

Configurable time borrowing flip-flops

A staggered logic array block (LAB) architecture can be provided. An integrated circuit (IC) device can include a first group of LABs substantially aligned with each other, and a second group of LABs substantially aligned with each other and coupled to the first group of LABs by a plurality of horizontal and vertical conductors. The first group of LABs can be substantially offset from the second group of LABs in the IC layout. In an embodiment of the invention, the first and second groups of LABs can be columns of LABs, and the columns can be vertically offset from each other (e.g., by half the number of logic elements in each LAB). The offsetting can advantageously allow more LABs to be reached using a single routing channel, or without using any routing channel, thereby reducing communication latency and improving overall IC performance.

Staggered logic array block architecture

A programmable logic device ('PLD') architecture includes logic elements ('LEs') grouped together in clusters called logic array blocks (LABs&#x201d;). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LAB) are reduced or eliminated as compared to in the prior art. Because all (or at least more) of any LE-output-to-LE-input connections of LEs that are working together in a LAB must be routed through the general-purpose input routing resources of the LAB, it is important to conserve those resources. This is accomplished, for example, by giving greater importance to finding logic functions that have common inputs when deciding what logic functions to implement together in a LAB.

Programmable logic device architectures and methods for implementing logic in those architectures

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Toronto, Canada

David Cashman