Altera Corporation

Pts Corporation

Other

Research Triangle Institute

Bops, Incorporated

Billions of Operations Per Second

David Carl Strube

Gerald George Pechanek

Grayson Morris

Edward A Wolff

Ricardo E Rodriguez

Dale Edward Schneider

Carl Donald Busboom

Patrick Rene Marchand

Edwin Franklin Barry

Edwin Frank Barry

Nikos P Pitsianis

Charles W Kurak, Jr

Marco Jacobs

Kevin Coopman

Matthew Plonski

Thomas L Drabenstott

Marco C Jacobs

Juan Guillermo Revilla

Jamie Shorey

Ann Pitruzzello

Barbara Kroner

An apparatus, system, and method are disclosed for detecting seizure symptoms in an individual. A sensor modulereceives physiological data for an individualfrom one or more sensors, such as a heart activity sensor. A feature detection moduledetects a predefined featurein the physiological data. The predefined featureis associated with a seizure or another medical condition. An alert modulebroadcasts an alert in response to the feature detection moduledetecting the predefined feature

Apparatus, system, and method for seizure symptom detection

Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.

Methods and apparatus for efficient complex long multiplication and covariance matrix implementation

Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.

System core for transferring data between an external device and memory

A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory (VIM) is employed along with execute and delimiter instructions. A masking mechanism may be employed to control which PEs have their VIMs loaded. Further, a receive model of operation is preferably employed. In one aspect, each PE operates to control a switch that selects from which PE it receives. The present invention addresses a better machine organization for execution of parallel algorithms that reduces hardware cost and complexity while maintaining the best characteristics of both SIMD and MIMD machines and minimizing communication latency. This invention brings a level of MIMD computational autonomy to SIMD indirect Very Long Instruction Word (iVLIW) processing elements while maintaining the single thread of control used in the SIMD machine organization. Consequently, the term Synchronous-MIMD (SMIMD) is used to describe the present approach.

Methods and apparatus for efficient synchronous MIMD operations with IVLIW PE-TO-PE communication

Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.

Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions

A system core having an internal memory which transfers data from an external device to the internal memory is described. To this end, the system core includes a processor, a direct memory access (DMA) controller, an instruction memory and a plurality of memories. The instruction memory contains processor instructions and DMA instructions. The DMA controller fetches DMA instructions from the instruction memory. The DMA controller executes the fetched DMA instructions and thus populates the plurality of memories with data from the external device. The processor then operates on the data found in the populated memories.

The ManArray core indirect VLIW processor consists of an array controller sequence processor (SP) merged with a processing element (PE0) closely coupling the SP with the PE array and providing the capability to share execution units between the SP and PE0. Consequently, in the merged SP/PE0 a single set of execution units are coupled with two independent register files. To make efficient use of the SP and PE resources, the ManArray architecture specifies a bit in the instruction format, the SP/PE-bit, to differentiate SP instructions from PE instructions. Multiple register contexts are obtained in the ManArray processor by controlling how the array SP/PE-bit in the ManArray instruction format is used in conjunction with a context switch bit (CSB) for the context selection of the PE register file or the SP register file. In arrays consisting of more than a single PE, the software controllable context switch mechanism is used to reconfigure the array to take advantage of the multiple context support the merged SP/PE provides. For example, a 1&#xd7;1 can be configured as a 1&#xd7;1 with context-0 and as a 1&#xd7;0 with context-1, a 1&#xd7;2 can be configured as a 1&#xd7;2 with context-0 and as a 1&#xd7;1 with context-1, and a 1&#xd7;5 can be configured as a 1&#xd7;5 with context-0 and as a 2&#xd7;2 with context-1. Other array configurations are clearly possible using the present techniques. In the 1&#xd7;5/2&#xd7;2 case, the two contexts could be a 1&#xd7;5 array (context-0) and a 2&#xd7;2 array (context-1).

Methods and apparatus for providing context switching between software tasks with reconfigurable control

Efficient techniques for computation of texture coordinates using scaled conversion operations for a 3D graphics pipeline utilizing a scaled floating point to integer instruction and a scaled integer to floating point instruction to significantly reduce memory requirements. A parallel array VLIW digital signal processor is employed along with specialized scaled conversion instructions and communication operations between the processing elements, which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the graphics pipeline hardware to be efficiently used.

Processor efficient transformation and lighting implementation for three dimensional graphics utilizing scaled conversion instructions

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Raleigh, NC, United States of America

David Carl Strube