Asahi Kasei Microdevices Corporation

Koninklijke Philips Corporation N.v.

U.S. Philips Corporation

Stepmind

David Canard

Vincent Fillatre

Cedric Morand

Fabrice Jovenin

Sebastien Charpentier

Matthieu Lecuyer

Julien Delorme

Fabrice Pichard

Sébastien Charpentier

A digital phase-locked loop (PLL) device includes a digital loop filter which is provided with both a VCO-loop output and a DCO-loop output. The VCO-loop output is connected to an analog input of a multiband voltage-controlled oscillator (VCO) module for allowing usual operation of the PLL with a direct voltage acting as feedback parameter. The DCO-loop output is connected to a digital control input of the multiband VCO module for allowing automatic frequency range selection. A code value which is produced by the digital loop filter acts as feedback parameter during the frequency range selection. Rapid and precise range selection can thus be performed.

Digital phase-locked loop device with automatic frequency range selection

There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.

Time-to-digital conversion with analog dithering

A phase frequency detector realizes a highly linear conversion from noise-shaped &#x3a3;&#x394; modulation into charge quantities without degradation of phase-locked loop (PLL) phase noise. The phase frequency detector may feature a construction of an Up signal output and a Down signal output, in which the Up signal rises when a divided VCO input rises, an Up signal falls when the divided VCO input falls, a Down signal rises when the divided VCO input rises, and a Down signal falls when a reference input rises. A mode selection input may be utilized for a fast lock-up PLL.

High-linearity phase frequency detector

A phase-locked loop device is configured to manage a transition from a relaxation-oscillation mode to a random noise operation mode. It is designed for progressively reducing proportional and integral coefficients that are implemented in a loop filter of the PLL device. Recovering the last values formerly used for the proportional and integral coefficients is also provided, in case the PLL lock state is lost. Such transition management may be combined with using a voltage-controlled oscillator within the PLL device, which has several control inputs.

Phase-locked loop device with managed transition to random noise operation mode

A variable modulus sigma delta (&#x3a3;&#x394;) modulator for a fractional-N frequency synthesizer in accordance with the present invention may include an integer division unit; a pulse-width modulation (PWM) generator, a &#x3a3;&#x394; noise-shaping unit, a first input FRAC for receiving a first programmable integer, and a second input MOD for receiving a second input, wherein the integer division unit is configured to perform a translation from the first input and the second input into a first output FRAC' and a second output R, the PWM generator is configured to receive the second input MOD and the second output R, and generate a modulated pulse signal, and the &#x3a3;&#x394; noise-shaping unit is configured to receive the first output and the modulated pulse signal, and generate a sequence whose average equals approximately the first input over the second input.

Variable modulus modulator for fractional-N frequency synthesizers

A fractional-N frequency synthesizer having a cancellation system for phase discontinuity due to loop gain changes may include a phase detector, a current-changeable charge-pump, a loop filter for providing a tuning signal, a voltage-controlled oscillator (VCO) controlled by the tuning signal for providing a VCO output signal, a divider for providing a divided VCO signal, a modulator for generating a modulating signal for fractional-N functionality, wherein the phase detector has a first input for receiving a reference signal oscillating at a reference frequency; a second input for receiving the divided signal; and the phase detector and charge-pump is configured to compare a phase of the first input and a phase of the second input, and generate a charge-pump current on and off, featuring that the cancellation system is implemented inside the modulator having an additional input defined by the changeable charge-pump current values.

Cancellation system for phase jumps at loop gain changes in fractional-N frequency synthesizers

The phase and frequency comparator for controlling, as a function of the frequency (F) and the phase of a reference signal (S), the frequency (F) and the phase of the output signal of a controlled-frequency oscillator comprises means () for detecting in the reference signal (S) and in the signal from the oscillator events representative of the frequency and the phase of that signal, means (S, S) for generating a first or second signal on the detection of an event, means (S, Sto) for generating a third or fourth signal on the detection of an event, if the first or second signal, respectively, is generated, means for applying all of the signals (I; V) generated to the oscillator, and means () for halting the generation of the first and second signals or of all of the signals if the first and second signals or the third and fourth signals, respectively, are generated simultaneously.

Method and a device for phase and frequency comparison

A mixer circuit with image frequency rejection comprising a quadrature phase divider (') presenting an input connected to the input (F) of the mixer circuit and two outputs respectively delivering two signals in phase quadrature which are applied respectively to two simple mixers (&#x2032;), said mixer circuit comprising a quadrature phase and frequency divider (&#x2032;) having a frequency division ratio and presenting two inputs respectively connected to the respective outputs of the two simple mixers (&#x2032;) and a first output delivering a first output signal (F) of the mixer circuit, which signal is applied to the inputs of the two simple mixers.

Mixer circuit with image frequency rejection, in particular for an RF receiver with zero or low intermediate frequency

The present invention relates to a device for comparison CMP, which is designed to emit a control signal Vcnt, which is representative of a difference which exists between the input signal frequencies Vdiv and Vref. The device according to the invention includes a phase/frequency comparator PD, which supplies a regulation signal Tun, which is subjected to pulse width modulation according to the difference observed. The device also includes a current source, which is designed to emit a charge current Ics, with a value which is controlled by the regulation signal Tun. The device further includes a capacitive element Cs, which is designed to generate the control signal Vcnt, under the effect of the charge current Ics. By means of a regulation signal Tun, which has a frequency which is virtually constant, the invention makes it possible to impose high-frequency variations on the control signal Vcnt.

Device for comparison of frequencies with low temporal inertia

The invention relates to a frequency converter FCV comprising a frequency divider FRACN, and an input port REG intended to receive a control word N(1:L) which determines a division ratio between the input FLO and output FDIV frequencies of the frequency divider FRACN. The frequency converter in accordance with the invention FCV additionally comprises interface means INT, arranged between the input port REG and the frequency divider FRACN, and intended to carry out a conversion of a control word value N(1:L) to a first and a second parameter M(1:L-P) and k(1:P) which jointly define a non-integer value of the division ratio of the frequency divider FRACN. The invention enables the user to program the frequency divider FRACN by means of a unique control word N(1:L), while customarily two control words are necessary to program non-integer division ratios.

Frequency converter enabling a non-integer division ratio to be programmed by means of a unique control word

Phase-locked loop enabling the generation of a reference signal having a high spectral purity

A frequency divider DIV/4 composed of memory cells (DL1 . . . DL4) realized in ECL technology, whose data paths constitute a loop, the data output Q4 of the last memory cell DL4 being cross-connected to the data input D1 of the first memory cell DL1. The clock inputs Ck of the memory cells DL1, DL3 of the odd rank are connected to the input IN of the frequency divider circuit DIV/4, while the others are cross-connected to said input. Such a frequency divider generates a noise having a unique frequency which is twice the frequency of the input signal, irrespective of the division ratio obtained.

Low-noise frequency divider

A controlled current source is disclosed which receives a control signal and supplies a current at an output. The current source includes a power module having a plurality of parallel-arranged power transistors, whose collectors are jointly connected to the output of the current source, a control module to receive the control signal, and an output to supply a signal enabling the power transistors to be turned on, wherein, the emitters of the power transistors are jointly connected to the output of the control module, the output for supplying a current whose value depends on the value of the control signal, the bases of the power transistors being permanently subjected to a voltage of a predetermined value enabling the power transistors to be rendered potentially conducting. By pre-charging the parasitic capacitances of the power transistors, the transistors are turned on at an accelerated rate.

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Caen, France

David Canard