Cradle Technologies, Inc.

Microsoft Technology Licensing, LLC

Brunswick Bowling & Billiards Corporation

Integrated Device Technology, Inc.

Advanced Micro Devices Corporation

Raytheon Company

Sri International

Quality Semiconductor Inc.

David C Wyland

Gerald A Pierce

David L Mowers

David J Mueller

Santo A Lamantia

Bruce N Alleshouse

Victor S Barczyk

Jonathan Alan Dutra

Lawrence E Demar

Agustya Ruchir Mehta

Paul G Dussault

David A Harrison

David Simon Lukofsky

Junius Mark Penny

Zwie Amitai

A dynamic power control circuit is provided. The control circuit can detect the presence of the external power source as well as detect one or more conditions of the device. For instance, the control circuit can detect a voltage difference between a first node coupling a first power output and a system circuit and a second node coupling a second power output and the batteries. The control circuit can also detect the activation or deactivation of the external power source. Based on the inputs, the control circuit can cause the controlled resistor to dynamically adjust a level of impedance between the first node and the second node. The controlled impedance between the first node and the second node enables the system circuit to dynamically utilize power supplied by the external power source as well as power supplied by the batteries.

Dynamic power control circuit

In accordance with certain embodiments of the present technology, edges of light drive pulses, which are produced by a light source driver and are used to drive a light source, are aligned with edges of light reference pulses that have a predetermined fixed delay relative to light timing pulses. This way, light pulses are emitted by the light source at precisely known times, so that accurate time-of-flight (TOF) measurements can be made. Additionally, edges of shutter drive pulses, which are produced by a shutter driver and are used to drive a gated light detector, are aligned with edges of shutter reference pulses that have a predetermined fixed delay relative to shutter timing pulses. This way, the gated light detector is shuttered on at precisely known times, so that accurate TOF measurements can be made.

Time-of-flight (TOF) system calibration

A large-power insulated gate switching device (e.g., MOSFET) is used for driving relatively large surges of pulsed power through a load. The switching device has a relatively large gate capacitance which is difficult to quickly discharge. A gate charging and discharging circuit is provided having a bipolar junction transistor (BJT) configured to apply a charging voltage to charge the gate of the switching device where the BJT is configured to also discontinue the application of the charging voltage. An inductive circuit having an inductor is also provided. The inductive circuit is coupled to the gate of the switching device and further coupled to receive the charging voltage such that application of the charging voltage to the inductive circuit is with a polarity that induces a first current to flow through the inductor in a direction corresponding to charge moving away from the gate and such that discontinuation of the application of the charging voltage to the inductive circuit induces a second current flowing through the inductor in the direction corresponding to charge moving away from the gate such that the second current discharges the gate of the switching device. Faster turn off of the switching device is thus made possible and is synchronized to the discontinuation of the charging voltage.

Insulated gate device discharging

A power switching device (e.g., a power MOSFET) drives relatively large surges of pulsed power through a laser emitter of a Time of Flight (TOF) determining system where both the power switching device and laser emitter are closely packed on a printed circuit board having further closely packed and temperature sensitive other components. Waveforms of pulse trains that control the power switching device are programmably defined and thus may include pulse durations that are unduly large or spacing between pulses that are unduly small such that overheating may occur. A pulse duration limiting circuit is provided having an analog integrator configured to integrate over time, the programmably defined pulses and a voltage triggered clamping device coupled to an output of the analog integrator. The voltage triggered clamping device has a predetermined threshold voltage at and above which it is switched from a relatively low transconductances mode to a substantially higher transconductances mode. The voltage triggered clamping device is coupled to a current supplying circuit branch of the system, the current supplying circuit branch being one that has an ability to supply current for switching on the power switching device.

Analog limit on digitally set pulse widths

Described herein are methods and subsystems for use with a timing generator having an output driver at which a timing signal having timing pulses is output. A method includes controlling the timing generator to cause the output driver to output a timing signal having an expected duty cycle, and filtering the timing signal to produce a DC voltage having a magnitude indicative of an actual duty cycle of the timing signal. The method also includes converting the DC voltage to a digital value indicative of the actual duty cycle of the timing signal. The method can also include comparing the digital value to an expected value corresponding to the expected duty cycle, and using results of the comparing to determine an error associated with the timing generator and/or produce a calibration table that can be used to calibrate the timing generator and/or calibrate a measurement made using the timing generator.

Precision measurements and calibrations for timing generators

A power supply is configured to automatically and rapidly switch from a voltage maintaining mode to a current limiting mode (at times that are unpredictable from a point of view of the power supply) when supplying replenishing current to a combination of a power insulated gate switching device and power capacitor that drive relatively large surges of pulsed power through a load such as a laser emitter of a Time of Flight (TOF) determining system. The current limiting mode is automatically activated by the start of each train of large surges of pulsed power and it replenishes charge to the power capacitor on a time averaged basis such that the capacitor develops a temperature appropriate voltage for providing the time averaged current to the power insulated gate switching device and its load and causing the load (e.g., laser) to output a desired amount of output power. The current limiting mode automatically stops when the time averaged current is detected to drop below a threshold and then the voltage maintaining mode automatically begins. The voltage maintaining mode maintains a stored voltage across the capacitor slightly greater than a maximum voltage needed to drive the load (e.g., laser emitter) to the desired magnitude of output power (e.g., output luminance).

Power regulator having current and voltage modes

Disclosed is a reprogrammable I/O system for a chip or board system that can be reprogrammed to simulate many I/O interfaces in firmware. The reprogrammable I/O system comprises an I/O cluster, an I/O bus, I/O pins, and logic at the I/O pins. The I/O pins are arranged logically in a row and are grouped into pin groups of eight pins. Each pin group also includes a pin state machine (PSM) and a data FIFO coupled together. Each PSM has chain connections to the two neighboring PSM's. Each data FIFO has chain connections to the two neighbor data FIFO's. The reprogrammable I/O system allows firmware to organize the I/O pins into I/O interfaces. The firmware in PSM's and the I/O cluster that control the operations of the I/O pins can be changed (reprogrammed) so that the I/O system can perform other different interfaces.

Reprogrammable input-output pins for forming different chip or board interfaces

A Bus Analyzer Unit (BAU) for performing trace analysis on either or both the global bus (GBus) or the I/O bus of a semiconductor chip. The BAU has a GBus trace unit and an I/O bus trace unit, each with its own trace logic. Each unit has filters and comparators which determine what data is recorded and when it is recorded. Trace data recorded by the units is written to a programmable, circular trace buffer in local memory or an SDRAM. Each trace unit has two registers holding the start and end addresses of the trace buffer. Each unit has a next address register containing the next address to which data may be written. As data is written, the next address register is incremented. When the next address register equals the value in the end address register, the next address register is reloaded with the address in the start register.

Bus analyzer unit with programmable trace buffers

Disclosed is a multiprocessor system including a semaphore register and a semaphore interrupt register. In addition, for each processor in the multiprocessor system, there is a semaphore interrupt enable register. If a first processor finds that a semaphore cell of the semaphore register holds a '1' indicating that an associated shared resource is being accessed by a second processor, the first processor sets a corresponding semaphore interrupt enable cell of the semaphore interrupt enable register to '1' so as to enable semaphore interrupt. When the second processor finishes with the shared resource, the second processor writes a 0 into the semaphore cell, causing a corresponding semaphore interrupt cell of the semaphore interrupt register to hold a &#x201c;1&#x201d;. This, combined with the fact that the semaphore interrupt enable cell also holds a &#x201c;1&#x201d;, causes an interrupt to the first processor. In response, the first processor services the interrupt and accesses the shared resource. As a result, repetitive reading and writing the semaphore cell by the first processor via a system bus of the multiprocessor system can be avoided.

Semaphores with interrupt mechanism

An error checking circuit that performs RS encoding and decoding operations and also generates CRC codes includes a configurable two-stage combinatorial circuit that carries out selected finite-field arithmetic operations associated with RS and CRC coding. Input registers store the generator polynomial and operand coefficients associated with the data blocks or packets being encoded or decoded, and an output register holds the intermediate working result and at the end the final result of the finite-field arithmetic operation. Each stage of the combinatorial circuit includes sets of AND and XOR gates performing bitwise finite-field multiply and add on the operand bits, and the connections between registers and gates and between gates in the two stages are configured by multiplexer units responsive to RS and CRC instructions. The two-stage combinatorial block can be replicated into a 4-stage or 8-stage arithmetic circuit for CRC mode.

Combined cyclic redundancy check (CRC) and Reed-Solomon (RS) error checking unit

Disclosed is a bus arbitration system and method which assume that each operation using the bus requires from one to five bus clock cycles. Each potential bus master has a dedicated bus request line and a dedicated bus grant line, both of which are connected to a centralized bus arbiter in the bus arbitration system of the present invention. When a potential bus master wants to use the bus for, for instance, three bus clock cycles, the bus master activates its dedicated bus request line for the same number of bus clock cycles as it would need of bus use (i.e. three bus clock cycles). This three clock wide bus request pulse is recorded in a bus request recording circuit in the centralized bus arbiter. Access to the bus can be granted by the centralized bus arbiter to a winning bus master under any bus arbitration policies. If a potential bus master is chosen to be the winning bus master, the centralized bus arbiter activates the winning bus master's dedicated bus grant line for the same number of bus clock cycles as requested by the bus master, i.e. for three bus clock cycles. So, the bus master will have sufficient use of the bus for its desired operation. After that, the arbiter chooses the next winning bus master and activates its dedicated grant line in the same manner described above, and so on.

Bus arbitration system and method for carrying out a centralized arbitration with independent bus request and grant lines

A digital system having a split transaction memory access. The digital system can access data from a system memory through a read buffer (FIFO) located between the processor of the digital system and the system bus. The read buffer is implemented with two FIFOs, a first incoming data FIFO for reading data, and a second outgoing address FIFO for transmitting read requests. The processor of the digital system can access the data FIFO and read data while the data transfer is still in progress. This decreases the processing latency, which allows the processor to be free to perform additional tasks.

Digital system with split transaction memory access

A system and method for finding available memory space associated with an inactive memory transfer controller and activating the inactive memory transfer controller using indexed addressing. A memory transfer engine includes a plurality of memory transfer controllers, each configured to move data from a source address to a destination address. An active memory transfer controller can execute an instruction to find an inactive memory transfer controller associated with available memory space. The inactive memory transfer controller is activated by writing to its hardware registers, thereby assigning it a task, using indexed addressing.

Finding available memory space by finding its associated memory transfer controller

Methods for waking up an idle memory transfer controller (MTC) in response to an event from an external source. The first mechanism, Parameter List Pointer (PLP) FIFO Wake Up, wakes up an MTC after an external agent writes to an MTC's PLP FIFO. This activates the MTC's run bit, making the MTC eligible to execute instructions if chosen to do so by the memory transfer engine arbiter. This mechanism allows the MTC to distinguish between multiple possible originators of multiple possible wake-up events; wake-up events may be queued. Events may be directed to particular MTCs or to the next MTC available to process the event. The second mechanism wakes up an MTC after an external agent writes to an MTC's external wake-up address. This sets the MTC's run bit, making the MTC eligible to execute instructions if chosen to do so by the memory transfer engine arbiter. This approach only recognizes one event and one source. Events may not be queued using this approach.

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San Jose, CA, United States of America

David C Wyland