Tokyo Electron Limited

Molecular Imprints, Inc.

Freescale Semiconductor,inc.

David C Wang

Frank Y Xu

Dorel Ioan Toma

Eric M Lee

Jeffrey T Wetzel

Sidlgata V Sreenivasan

Edward Brian Fletcher

Michael P C Watts

Ian Matthew McMackin

Pankaj B Lad

Nicholas A Stacey

Van Nguyen Truskett

Dharmesh Jawarani

Ross Edward Noble

Kenneth Duerksen

David A Vidusek

Robert J Soave

Christopher J Mackay

Wesley D Martin

A method for making a semiconductor device is provided by (a) providing a substrate () having first () and second () gate structures thereon; (b) forming an underlayer () over the first and second gate structures; (c) removing the underlayer from the first gate structure; (d) forming a first stressor layer () over the first and second gate structures; and (e) selectively removing the first stressor layer from the second gate structure through the use of a first etch which is selective to the underlayer.

Dual interlayer dielectric stressor integration with a sacrificial underlayer film stack

The present invention includes a method and a composition to form a layer on a substrate having uniform etch characteristics. To that end, the method includes controlling variations in the characteristics of a solid layer, such etch characteristics over the area of the solid layer as a function of the relative rates of evaporation of the liquid components that comprise the composition from which the solid layer is formed.

Method to provide a layer with uniform etch characteristics

The present invention is directed to a method of etching a multi-layer structure formed from a layer of a first material and a layer of a second material differing from the first material to obtain a desired degree of planarization. To that end, the method includes creating a first set of process conditions to etch the first material, generating a second set of process conditions to etch the second material; and establishing an additional set of process conditions to concurrently etch the first and second materials at substantially the same etch rate.

Etching technique to planarize a multi-layer structure

The present invention features a method of patterning a substrate that includes forming from a first material, disposed on the substrate, a first film having an original pattern that includes a plurality of projections. The projections extend from a nadir surface terminating in an apex surface defining a height therebetween. A portion of the first film in superimposition with the nadir surface defines a nadir portion. The nadir portion is removed to expose a region of the substrate in superimposition therewith, defining a plurality of recessions. A second material is disposed upon the first film to form a second film having a surface spaced-apart from the apex surface of the plurality of projections and filling the plurality of recessions to form a multi-film stack. The first film and portions of the second film are removed to create a plurality of spaced-apart projections of the second material on the substrate.

Method of forming an in-situ recessed structure

An interconnect structure in back end of line (BEOL) applications comprising a tunable etch resistant anti-reflective (TERA) coating is described. The TERA coating can, for example, be incorporated within a single damascene structure, or a dual damascene structure. The TERA coating can serve as part of a lithographic mask for forming the interconnect structure, or it may serve as a hard mask, a chemical mechanical polishing (CMP) stop layer, or a sacrificial layer during CMP.

Structure comprising tunable anti-reflective coating and method of forming thereof

A method for forming a mechanically strengthened feature in a low-k dielectric film on a substrate includes using either spin-on-dielectric (SOD) techniques, or chemical vapor deposition (CVD) techniques to form a low-k dielectric film on the substrate. A sidewall of the feature in the low-k dielectric film is then treated in order to increase the film's mechanical strength. Treatment of the sidewall of the feature in the low-k dielectric film comprises forming a hardened layer by subjecting the low-k dielectric film to low energy, high flux ion implantation. Process parameters of the ion implantation are selected such that the implantation process does not cause a substantial change in the dielectric constant of the low-k dielectric film.

Method for using ion implantation to treat the sidewalls of a feature in a low-k dielectric film

A semiconductor device includes a semiconductor substrate, a film stack formed on the semiconductor substrate and having a film to be processed. A dual hard mask included in the film stack has an amorphous carbon layer and an underlying hard mask layer interposed between the amorphous carbon layer and the film to be processed, the hard mask layer does not include an amorphous carbon layer. A damascene structure for a metal interconnect is formed in the film stack. The amorphous carbon film can, for example, be incorporated within a single damascene structure, or a dual damascene structure. The amorphous carbon film can serve as part of a lithographic mask for forming the interconnect structure, or it may serve as a top layer of a dual hard mask, a chemical mechanical polishing (CMP) stop layer, or a sacrificial layer during CMP.

Structure comprising amorphous carbon film and method of forming thereof

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Austin, TX, United States of America

David C Wang