Chrontel Inc.

Chrontel International Ltd.

David C Soo

Tat C Choi

Lawrence Tze-Leung Tse

Meng Long

The present invention relates to methods of making and using and apparatus for providing touch screen capability using an LCD screen without an extra touch screen layer.

Methods of making and using an apparatus for providing multi-touch sensing capability using an LCD screen without an extra touch screen layer

A sub-system and method to receive input image pixel amplitude data at an input pixel resolution and to output image pixel amplitude data in one or two dimensions at a higher pixel resolution includes a computer system-executable algorithm with user-programmable coefficients. The programmable coefficients are user-selectable according to the nature and quality of the input image data such that sharpness of the output image data can be at least partially tailored to the image.

System and method for image scaling interpolation

A RAMDAC circuit drives a display device so as display multiple modes of color depth and display resolution in a single display frame without sacrificing resolution of the higher-resolution mode, and adjusts the output pixel rate to match that of the display mode being display on a pixel-by-pixel basis. The RAMDAC circuit switches between two graphics modes on-the-fly on a pixel-by-pixel basis in accordance with mode control bits stored in the pixel data. Furthermore, the RAMDAC circuit switches between two output pixel rates such that the amount of video memory used for any predefined screen area remains constant even though the output pixel rate and resolution are dynamically adjusted. In a preferred embodiment a display mode signal is embedded in the display data such that the display data, including the mode signal, comprises one byte of data for each display pixel when the mode signal specifies the first display mode, and comprises two bytes of data for each display pixel when the mode signal specifies the second display mode.

Method and apparatus for on-the-fly multiple display mode switching in

A phase-locked loop (PLL) circuit, manufacturable using standard integrated circuit technology, includes a sampled-data phase detector, a sampled-data loop filter for filtering the output of the phase detetector, a voltage controlled oscillator driven by the output of the loop filter, and a frequency divider in the feedback loop. A clock circuit generates reference signals needed by the other circuit components. The sampled-data phase detector, under the control of two clocks of differing frequencies, derives a phase error signal through the use of discrete-time analog integration of its input signal. When the PLL is in lock, this phase detector outputs valid phase error signal at discrete time intervals. The gain of the phase detector is proportional to a ratio of capacitor values, a ratio of frequencies, and a reference voltage, all of which can be made substantially independent of variations in temperature and semiconductor processing. A separate frequency acquisition circuit is used to prevent false locking of the PLL on an erroneous frequency. The outputs of this frequency acquisition circuit are fed to the loop filter by a switched-capacitor circuit arrangement that automatically removes the frequency acquisition circuit from the feedback loop once frequency acquisition has been achieved. The sampled-data loop filter emulates the response of continuous-time filters by replacing resistors with switched capacitors. The loop filter response is, to first order, a function only of capacitor ratios and the frequency of a reference clock.

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Milpitas, CA, United States of America

David C Soo