International Business Machines Corporation

David C Reynolds

Michael Wong

William C Leipold

Daniel Nelson Maynard

Mitchell R DeHond

Brian Douglas Pfeifer

Reginald B Wilcox, Jr

Martin C Green

Timothy W Budell

Eric W Tremble

Henry A Bonges, Iii

Bette L Bergman Reuter

David M Matheu

James E Sundquist

Betty L Bergman Reuter

Frederick H Rumpf

Theis Clarke

Dhaval Doshi

David Scott Crocker

After finding the shortest conductive signal return-current path for each signal, the invention assesses whether each conductive return-current path is adequate. The method analyzes each shortest conductive signal return-current path and determines if a significant portion of the signal return current flows as displacement current rather than following the conductive current path. A significant displacement current flows when the length of the conductive return-current path that diverges from a signal net is more than a previously defined limit based on the signal transition time. Further, a significant displacement current flows when the overall length of the signal differs from the overall length of the conductive return-current path by more than a previously defined limit based on the signal transition time.

Automatic verification of adequate conductive return-current paths

A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.

Physical design characterization system

A method of performing latch up check on an integrated circuit (IC) design that comprises rasterizing a conductor region shape and contact shapes and iteratively expanding the contact shapes within the conductor region shape using a cellular algorithm. Direction values for contact cells can be used to limit the number of neighboring cells which must be explored. In every fourth iteration of the expansion process, corner cells may not be expanded. Reachable areas outside of conductors can also be explored.

Method of performing latch up check on an integrated circuit design

Method for use in a CAD system whereby three-dimensional interferences among space-oriented objects can be rapidly determined by storing a reduced granularity of the design space in the form of a three-dimensional matrix having elements which represent identification numbers of objects which occupy the design space in the subcontinuum represented by the element. The element can be multidimensional or the element can refer to a table if more than one object occupies the associated subcontinuum. As objects are added to the drawing, the new objects are assigned unique index numbers which are stored in all the matrix elements corresponding to all the subcontinuums occupied by the object. Calculations for interference among pairs of objects need only be made between objects having their index number in a same element of the matrix.

Method for enhancing three-dimensional interference checking

Graphics display system having a moving cursor, such as a cursor, for selecting a displayed entity with the capability of determining which one of several lower level entities in the vicinity of the cursor is to be selected. The correlation of a cursor with a entity intended to be selected is performed by calculating an index that does not represent the actual distance, which is time consuming, but rather represents a value, more quickly calculated, such that the size order among the indices is the same as the size order of the distances they represent.

Fast point/line correlations in graphic entities

Graphics display system having a moving cursor, such as a cursor, for selecting a displayed entity. The correlation of a cursor with an entity intended to be selected is performed by storing a unique tag assigned to each entity in a cell in a correlation array related to a pel or group of pels corresponding to locations in a bit map of the pels comprising the entity. The x,y coordinates of the cursor are converted into a cell number corresponding to the bit map locations matching such x,y coordinates. The entity tag is then retrieved from the addressed cell.

Fast correlation of markers with graphic entities

Growing community of inventors

Essex Junction, VT, United States of America

David C Reynolds