Analog Devices,inc.

Mitsubishi Electric Research Laboratories, Inc.

Tundra Semiconductor Corporation

Other

National Semiconductor Corporation

David C Reynolds

Benjamin Vigoda

Alexander Alexeyev

Jeffrey G Bernstein

William Bradley

Eric G Nestler

Vladimir Zlatkovic

Jeffrey Venuti

Steven M Waldstein

Maurice Richard

Richard B Merrill

Darren L Leigh

William Yerazunis

Paul H Dietz

David H Robertson

Douglas A Mercer

Dirk Brinkman

Kevin J McCall

Ernest T Stroud

Doug R Farrenkopf

Jonathan Westhues

A circuit implementing a soft logical processing network includes an interconnection of analog processing elements, which can include soft logic gates, for instance soft Equals gates and soft XOR gates. In some examples, each of the soft logic gates include multiple circuit parts, with each part including an input configured to accept a voltage signal representation of a soft logical quantity, and a conversion section configured to use the accepted voltage representation to form a corresponding current signal. The current signals are combined to form a signal representation of the output of the gate. In an application of soft logic gates, a memory includes a group of electrical storage elements, each electrical storage elements carrying a respective storage values; a group of conversion elements, each conversion element being coupled to a respective electrical storage element for selectively converting the corresponding storage value to a current signal; and a current combination element for combining the current signals to form an output signal.

Circuits for soft logical functions

A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

Storage devices with soft processing

A processor includes a first memory module for storing a first set of storage values each representing a respective input, and a second memory module for storing a second set of storage values in analog form. An analog module is coupled to the first and the second memory modules. The analog module is configured to, in each operation cycle of at least one iteration, update at least some of the second set of storage values based on the first and the second sets of storage values. An output module is for generating a set of outputs from at least some of the second set of storage values.

Belief propagation processor

A processor implements a network of functional nodes and communication paths between the nodes. The processor includes a plurality of circuit implementations of the functional nodes of the processor; and a plurality of signal paths implementing the communication paths linking the circuit implementations of the nodes. At least some of the signal paths are configured to pass signal values represented according to temporal patterns of signal levels on the signal paths. The processor also includes a plurality of circuit components for conversion between a signal value represented as a signal level (e.g., voltage or current level) and a signal value represented as a temporal pattern.

Mixed signal stochastic belief propagation

A decoder control makes use of controllable transfer gates, which effectively implement selectors, to implement required timing offsets for codes that have particular structure. For instance, such timing offsets are effective for LDPC codes with block off-diagonal structure, for instance, as described in the co-pending application. In some implementations, the memory architecture is formed of cells where each cell includes not only a storage element, by also control logic that combines a select signal and the write versus read signal. By co-locating this control logic in each memory cell, control logic and its associated signal distribution is reduced, thereby reducing circuit area and power consumption.

Decoder control

In one aspect, a storage device includes a plurality of storage strings, each comprising a serial interconnection of a plurality of active storage elements, each storage element having a part for maintaining a storage state and a part of modulating a current through the element according to the storage state. The device also includes mapping circuitry for selectively sensing a storage state of a storage element in a storage string by forming current though the storage element that is a non-linear function of the storage state. In some examples, the mapping circuitry comprises reference string of active elements, and the mapping circuitry selectively senses a storage state by forming a difference in currents in the sensed storage string and in the reference string that is a non-linear function of the storage state. In some examples, the active storage elements comprise floating gate transistors.

Storage device architecture

A circuit implementing a soft logical processing network includes an interconnection of analog processing elements, which can include soft logic gates, the soft logic gates including one or more soft logic gates. In some examples, each of the soft logic gates include multiple circuit parts, with each part including an input configured to accept a voltage signal representation of a soft logical quantity, and a conversion section configured to use the accepted voltage representation to form a corresponding current signal. The current signals are combined to form a signal representation of the output of the gate.

An apparatus measures a fluid level in a container. A light source emits a light beam. A light sensor can sense the light beam. An optical conduit is arranged in a container for holding fluid. The optical conduit is arranged between the light source and the light sensor along a path of the light beam, such that at least one part of the light beam passes through the optical conduit, and at least an other part of the light beam passes through the fluid when the container holds the fluid. The sensor senses the light beam when a level of the fluid coincides with the one part of the light beam passing through the optical conduit, and the sensor does not sense the light beam when the level of the fluid coincides with the other part of the light beam passing through the fluid due to internal reflection at the fluid level.

Optical fluid level encoder

Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.

Physical layers

First and second clocked digital sources are provided in each of two data paths, and are clocked by respective direct and complementary clock pulses. The clocked outputs of these devices are directed to a multiplexer where the inter-leaved data path signals are recombined into a single output line. This multiplexer includes clocked transmission gates, the clock signals for which are shifted in time by 90&deg; from the clock signals applied to the originating signal sources. The result is that additional time is made available for sampling the digital signals applied to the multiplexer.

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David C Reynolds