Sun Microsystems, Inc.

Integrated Micro Products, Ltd.

David C Liddell

Emrys J Williams

Peter Heffernan

Rhod James Jones

Gary S Rumney

Michael J Bushue

Jeremy B Rolls

A computer system includes a chassis with a single motherboard supporting at least one processor module. A power sub-system receives three power supply units and distributes power within the computer system. Each of the three power supplies has a power rating such that two of the three power supplies are sufficient to power the computer system. The combination of such a single-motherboard-based design with a redundant three-power supply sub-system provides reliability of operation in a cost-effective manner. The power sub-system includes a power distribution board with power distribution logic operable to distribute power from the power supply units for powering the processor module. The power distribution logic is operable to interrupt power for powering the processor module when two of the power supply units fail or are not present. An alarm sub-system is provided for reporting power supply faults.

Powering computer systems

A computer system includes processing circuitry and alarm circuitry connectable to a network. A power sub-system includes at least three power supply units, wherein at least a predetermined plurality of power supply units are required to power the computer system. A power distribution mechanism is connectable to the power supply units. The power distribution mechanism is connected to the processing circuitry to supply main power thereto and is connected to the alarm circuitry to supply standby power thereto. The power distribution mechanism is operable to supply main power to the processing circuitry when at least a said predetermined plurality of connected power supplies are operative and is operable to supply standby power to the alarm circuitry when at least one power supply is operative. The power distribution mechanism enables power to be supplied to the alarm circuitry when only one power supply remains operative such that an alarm can still be reported over the network when the other power supply units have failed or are not present. The alarm circuitry also enables remote diagnostic functions to be performed from a remote location over the network.

Processing and alarm circuitries each having different power supply unit(s) requirement and powering the respective device when the corresponding requirements is met

A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules. Each central processing module contains a means by which the module can compare data on the main data bus with data on a secondary bus within each module in order to determine if there is an inconsistency indicating a hardware fault. If such an inconsistency is detected, each module generates state outputs which reflect the probability that a particular module is the source of the fault. A synchronization bus which is separate from the main data bus interconnects the central processing modules and transmits the state outputs from each module to every other central processing module.

System and method for driving a signal to an unbuffered integrated circuit

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System and method for preserving the state of a device across a reset event

System and method for providing synchronous clock signals in a computer

System and method for accessing devices in a computer system

System and method for iterative copying of read/write memory

System and method for self-referential accesses in a multiprocessor

System and method for synchronously resetting a plurality of

A system and method for tracking dirty memory which, in one embodiment, comprises a first memory corresponding to a first processor, a second memory corresponding to a second processor and a third memory coupled to the first memory, wherein the third memory stores bits corresponding to the pages of the first memory, and wherein each bit is set to 'dirty' when the first processor writes to the corresponding page of the first memory and is set to 'clean' when the corresponding page of the first memory is copied to a corresponding page of the second memory. The system and method can be used in a computer having multiple cpusets to assist in cpuset re-integration by copying the contents of one cpuset's memory to another cpuset's memory while the operating system of the computer continues to run.

System and method for tracking dirty memory

System and method for diagnosing errors in a multiprocessor system

System and method for reducing the effects of hardware faults in a

Method and apparatus for reducing the effects of hardware faults in a

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Gosforth, United Kingdom

David C Liddell