Bae Systems Information and Electronic Systems Integration Inc.

Lockheed Martin Corporation

Other

Ovonyx Inc.

Bae Systems Information and Electronics Systems Integration Inc.

David C Lawson

Bin Li

Tri Minh Hoang

Kenneth R Knowles

Livia L Zien

Jason F Ross

Scott Doyle

Shankarnarayana Ramaswamy

Edward Maher

Tatia B Butts

Dongho Lee

A sense amplifier for static random access memories is disclosed. The sense amplifier includes a pair of inverters cross-coupled to each other. The sense amplifier also includes means for equalizing the charges within the pair of inverters before performing a sense operation, and means for sensing a current difference between a bitline and its complement from a memory cell during the sense operation.

Sense amplifier for static random access memories

A single event upset (SEU) hardened memory cell to be utilized in static random access memories is disclosed. The SEU hardened memory cell includes a first transistor, a second transistor and a first resistor connected between a source of the first transistor and a drain of the second transistor. The SEU hardened memory cell also includes a third transistor, a fourth transistor and a second resistor connected between a source of the third transistor and a drain of the fourth transistor. The first resistor is also connected between a gate of the third transistor and the drain of the second transistor. The second resistor is also connected between a gate of the first transistor and the drain of the fourth transistor.

Single event upset hardened static random access memory cell

A single event upset (SEU) hardened memory cell to be utilized in static random access memories is disclosed. The SEU hardened memory cell includes a first inverter and a second inverter connected to each other in a cross-coupled manner. The SEU hardened memory cell also includes a first resistor, a second resistor and a capacitor. The first resistor is connected between an input of the first inverter and an output of the second inverter. The second resistor is connected between an input of the second inverter and an output of the first inverter. The capacitor is connected between an input of the first inverter and an input of the second inverter.

Apparatus for hardening a static random access memory cell from single event upsets

A read/write circuit for accessing chalcogenide non-volatile memory cells is disclosed. The read/write circuit includes a chalcogenide storage element, a voltage limiting circuit, a current-to-voltage converter, and a buffer circuit. The voltage limiting circuit, which is coupled to the chalcogenide storage element, ensures that voltages across the chalcogenide storage element will not exceed a predetermined value during a read operation. During a read operation, the current-to-voltage converter, which is coupled to the voltage limiting circuit, converts a current pulse read from the chalcogenide storage element to a voltage pulse. By sensing the voltage pulse from the current-to-voltage converter, the buffer circuit can determine a storage state of the chalcogenide storage element.

Read/write circuit for accessing chalcogenide non-volatile memory cells

A circuit for accessing a chalcogenide memory array is disclosed. The chalcogenide memory array includes multiple subarrays with rows and columns formed by chalcogenide storage elements. The chalcogenide memory array is accessed by discrete read and write circuits. Associated with a respective one of the subarrays, each of the write circuits includes an independent write 0 circuit and an independent write 1 circuit. Also associated with a respective one of the subarrays, each of the read circuits includes a sense amplifier circuit. In addition, a voltage level control module is coupled to the read and write circuits to ensure that voltages across the chalcogenide storage elements within the chalcogenide memory array do not exceed a predetermined value during read and write operations.

Circuit for accessing a chalcogenide memory array

A single event upset hardened latch circuit is disclosed. The single event hardened latch circuit includes a first dual-port inverter and a second dual-port inverter. An input is coupled to the first dual-port inverter via a first set of pass gates. The first dual-port inverter is coupled to the second dual-port inverter via a second set of pass gates. The output is connected to the first and second dual-port inverters.

Single event upset (SEU) hardened latch circuit

In a sense amplifier for reading out memory cells of a memory comprising a set of P-FETs and N-FETs, complementary input signals received from the memory cell being read out are applied to input junctions connected to gates of N-FETs. The input junctions are charged to 0.8 volts by a precharging circuit comprising P-FETs connecting the input junctions to ground and an N-FET shunting the input junctions together. The P-FETs and N-FETs of the precharging circuit are rendered conductive between memory cells readouts to precharge the input junctions and are rendered nonconducting during memory cell readouts. A second precharging circuit precharges an output junction of the sense amplifier circuit. The output junction is connected to an output amplification stage including a CMOS circuit. Because of the low equalization voltage to which the input junctions are precharged, the time to precharge the input junctions is dramatically reduced and a reduction in the memory access time is achieved.

Self-equalized low power precharge sense amp for high speed SRAMs

A single event upset hardened multiport memory cell to be utilized in a register file is disclosed. The single event upset hardened multiport memory cell includes a storage cell, a write bitline, a read bitline. The storage cell, which is utilized for storing data, includes first and second sets of cross-coupled transistors and first and second sets of isolation transistors. The first and second sets of isolation transistors are respectively coupled to the first and second set of cross-coupled transistors such that two inversion paths are formed between the two sets of cross-coupled transistors and the two sets of isolation transistors. Coupled to the storage cell, the write bitline inputs write data to the storage cell. Also coupled to the storage cell, the read bitline outputs read data from the storage cell.

Self-restoring single event upset (SEU) hardened multiport memory cell

A memory device includes a plurality of memory cells arranged in rows and columns. The memory cells are divided into a plurality of sub-arrays. The memory cell further includes a plurality of word lines connecting rows of the memory cells, and a plurality of bit line pairs connecting columns of the memory cells. An address transition detect (ATD) circuit detects an address transition for a selected memory cell and generates an ATD pulse in response thereto. A respective bit line precharge circuit is associated with each of the plurality of sub-arrays. An ATD pulse distribution circuit distributes the ATD pulse to only a selected sub-array containing the selected memory cell to activate only the bit line precharge circuit of the selected sub-array and not activate precharge circuits of other non-selected sub-arrays.

Memory device having reduced power requirements and associated methods

A memory device includes a plurality of address on-chip receivers (OCRs), an address decoder coupled to the address OCRs, a plurality of first delay circuits coupled between the address OCRs and the address decoder, and a plurality of chip select bypass circuits. Each chip select bypass circuit is respectively coupled to one of the plurality of first delay circuits for initially reducing a delay therein responsive to a control signal. The chip select bypass circuit includes a second delay circuit having a delay less than the first delay circuit, and a disable circuit. The disable circuit disables the first delay circuit and selectively couples the second delay circuit in place of the first delay circuit responsive to the control signal.

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Haymarket, VA, United States of America

David C Lawson