Advanced Micro Devices Corporation

Siemens Industry, Inc.

David C Horton

Wei-Lien Hsu

Amit R Gupta

Yi Liu

A method is disclosed for performing a discrete cosine transform (DCT) using a microprocessor having an instruction set that includes SIMD floating point instructions. In one embodiment, the method includes: (1) receiving a block of integer data having C columns and R rows; and (2) for each row, (a) loading the row data into registers; (b) converting the row data into floating point form so that the registers each hold two floating point row data values; and (c) using SIMD floating point instructions to perform weighted-rotation operations on the values in the registers. Suitable SIMD floating point instructions include the pswap, pfmul, and pfpnacc instructions. For the row-DCT, the data values are preferably ordered in the registers so as to permit the use of these instructions. For the column-DCT, two columns are preferably processed in parallel using SIMD instructions to improve computational efficiency. An intermediate buffer may be used to avoid unnecessary conversions between integer and floating point format.

Two-dimensional discrete cosine transform using SIMD instructions

A method is disclosed for performing an inverse discrete cosine transform (IDCT) using a microprocessor having an instruction set that includes SIMD floating-point instructions. In one embodiment, the method includes: (1) receiving a block of integer data having C columns and R rows; and (2) for each row, (a) loading the row data into registers; (b) converting the row data into floating-point form so that the registers each hold two floating-point row data values; and (c) using SIMD floating-point instructions to perform weighted-rotation operations on the values in the registers. Suitable SIMD floating-point instructions include the pswap, pfmul, and pfpnacc instructions. For the row-IDCT, the data values are preferably ordered in the registers so as to permit the use of these instructions. For the column-IDCT, two columns are preferably processed concurrently using SIMD instructions to improve computational efficiency. An intermediate buffer may be used to avoid unnecessary conversions between integer and floating-point format.

Two-dimensional inverse discrete cosine transform using SIMD instructions

A method for performing Fast (forward or inverse) Fourier Transform in a micro-processor-based computer system. The microprocessor includes parallel execution resources for executing parallel floating-point addition, subtractions and multiplication operations on the contents of a specialized set of internal registers. The method comprises performing computations associated with two adjacent butterflies simultaneously and in parallel. Thus, data operands are accessed, and computational results are stored, from/to memory in pairs. Furthermore, the ordering and arrangement of program instructions is optimized with respect to the execution resources available in the microprocessor. Care is taken to avoid potential stalling conditions. A processor simulator is used to anticipate and avoid potential resource conflicts. For example, instructions which require a common execution resource may be separated with one or more intervening instructions which utilize different execution resources. In addition, alignment instructions are inserted in strategic position within code sequences to guarantee proper alignment of subsequent instructions with cache lines. The first two passes and the last pass of the FFT algorithm are computed separately.

System and method for high speed execution of Fast Fourier Transforms utilizing SIMD instructions on a general purpose processor

A method and circuit is provided for preloading a branch prediction unit within a microprocessor. In one embodiment of the method, a branch history storage device such as branch history shift register is written with a predetermined multibit predicter in response to the microprocessor receiving and executing a special write branch history storage device instruction for writing the predetermined multibit predicter into the branch history storage device. The branch history storage device is contained within a prediction circuit of the microprocessor, and generally the contents of the branch history storage device is used in the process of predicting the results of executing conditional branch instructions prior to their execution. Once the branch history storage device is preloaded with the predetermined multibit predicter, the prediction circuit predicts the result of a conditional branch instruction using the predetermined multibit predicter stored in the history device after the conditional branch instruction is received by the microprocessor and before the conditional branch instruction is executed. In one embodiment, the predetermined multibit predicter is an operand of the write history storage device instruction received and executed by the microprocessor.

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Austin, TX, United States of America

David C Horton