Freescale Semiconductor,inc.

Motorola Corporation

David C Holloway

Michael D Snyder

Marvin A Denman

Gary L Whisenhunt

Bradley Gene Burgess

Trinh Huy Nguyen

Jeffrey Pidge Rupley, Ii

Suresh Kumar Venkumahanti

Sergio Schuler

A processing device includes a storage component configured to store instructions associated with a corresponding thread of a plurality of threads, and an execution unit configured to fetch and execute instructions. The processing device further includes a period timer comprising an output to provide an indicator in response to a count value of the period timer reaching a predetermined value based on a clock signal. The processing device additionally includes a plurality of thread forward-progress counter components, each configured to adjust a corresponding execution counter value based on an occurrence of a forward-progress indicator while instructions of a corresponding thread are being executed. The processing device further includes a thread select module configured to select threads of the plurality of threads for execution by the execution unit based a state of the period timer and a state of each of the plurality of thread forward-progress counter components.

Forward progress mechanism for a multithreaded processor

A thread switch mechanism and technique for a microprocessor is disclosed wherein a processing of a first thread is completed, and a continuation of a second thread is initiated during completion of the first thread. In one form, the technique includes processing a first thread at a pipeline of a processing device, and initiating processing of a second thread at a front end of the pipeline in response to an occurrence of a context switch event. The technique can also include initiating a instruction progress metric in response the context switch event. The technique can further include enabling completion of processing of instructions of the first thread that are at a back end of the pipeline at the occurrence of the context switch event until an expiry of the instruction progress metric.

Completion continue on thread switch based on instruction progress metric mechanism for a microprocessor

A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.

Multiple address and arithmetic bit-mode data processing device and methods thereof

A branch prediction unit apparatus and method uses an instruction buffer ( ), a completion unit ( ), and a branch prediction unit (BPU) ( ). The instruction buffer ( ) and/or the completion unit ( ) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers ( ). The SID bits are used to associate the pending and executing instructions in the units ( and ) into instruction streams related to predicted branches located in the buffers ( ). The SID bits as well as age bits associated with the buffers ( ) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.

Apparatus and method for predicting multiple branches and performing out-of-order branch resolution

A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.

Growing community of inventors

Cedar Park, TX, United States of America

David C Holloway