Digital Equipment Corporation

Commscope Technologies LLC

Acuity Imaging, LLC

David C Davies

Michael J Wilt

Michael Philip Greenberg

Michael Pollman

Donald G Vonada

Kevin E Craig

John E Agapakis

Robert A Curtis

Stephen Ledingham

MIMO antenna modules and antenna units for a wireless communication system are provided. In one embodiment, a remote unit comprises: a controller module, comprising: a first substrate having a first ground plane, control circuitry and interface circuitry on the first substrate, a first connection region formed in the first substrate; and at least one antenna module coupled to the controller module, the antenna module comprising: a second substrate having a second ground plane, antennas on the second substrate, a second connection region on the second substrate and coupled to the interface circuitry via the first connection region, wherein the second connection region communicates data between the interface circuitry and the antennas, and a set of ground-plane contacts on the second substrate that electrically couple the first ground plane to the second ground plane of the second substrate when the second connector region is engaged with the first connector region.

MIMO antenna module and MIMO antenna unit for distributed antenna system

An embodiment of an antenna module includes a substrate, a first antenna, and a second antenna. The first antenna is disposed on the substrate and is configured to radiate a first signal having a wavelength and a first polarization. And the second antenna is disposed on the substrate and is configured to radiate a second signal having the wavelength and a second polarization that is approximately orthogonal to the first polarization. For example, such an antenna module can include, as the first antenna, a T antenna configured to transmit and receive data that forms a first part of a MIMO-OFDM data symbol, and can include, as the second antenna, an F antenna configured to transmit and receive data that forms a second part of the MIMO-OFDM data symbol.

A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices. The architecture provides a method of loading an embedded system CPU's local memory with operating system and diagnostic code without the use of ROM or FLASH memory. A system and method of reserving memory is also disclosed which utilizes a dummy or surrogate board with little of no functionality but which has a class code of a common device such as an Ethernet card. The primary system BIOS will read the class code and reserve memory based on the surrogate card. The driver of the non-standard card such as an embedded processor, can then use the memory space allocated to the surrogate card by the BIOS.

Flexible processing hardware architecture

A peak detector circuit employs a line receiver of the ECL type, with the analog input signal to be tracked as a receiver input. The other receiver input is connected to the circuit output. A capacitor connects the output node of the circuit to threshold reference voltage input. The capacitor is charged through a resistor from the output of the line receiver when the input signal exceeds the voltage on the output node, and the capacitor discharges to the reference input through this resistor and another resistor connecting the receiver output to the reference input. The output voltage tracks the peaks of the input signal. Oscillation of the receiver is avoided by using a threshold reference greater than zero. The dynamic range of the output can be extended to a level higher than that of ECL levels by summing the thresholds of a number of these detectors, using an operational amplifier.

Tracking peak detector

Transceiver apparatus includes a transmitter circuit constructed with either emitter coupled logic (ECL) circuitry or programmable array logic circuitry, and a receiver circuit constructed with ECL circuitry. The transmitter circuit encodes a binary data signal received for transmission as a three-level modified duobinary encoded data signal and the receiver circuit decodes the received three-level encoded data signal to provide a binary data signal corresponding to the data signal received at the transmitter circuit for transmission. Both the transmitter and receiver circuits include features enabling transmitting and receiving high data-rate data signals.

Transceiver apparatus and methods

In a serial data communications system, an embedded clock is recovered from a data signal by incrementally controlling the frequency (thus phase) of a voltage-controlled oscillator in response to the difference in phase between the incoming data signal and the clock oscillator output. A transition of the data signal is detected and used to initiate a control pulse which is terminated upon the next transition in the clock oscillator output. A reference pulse is also generated which has a width about equal to a half cycle of the clock. These pulses are used to generate the voltage control for the oscillator, so that the phase relationship varies to see an equilibrium where the pulses are of equal width and the transitions of the clock are at midpoint of potential transitions of the data signal. The control can tolerate relatively long periods where there is no transition of the data signal. The control circuitry includes a counter for counting transitions of the clock to inhibit another detect operation from starting until three transitions after one has begun.

Growing community of inventors

Chelmsford, MA, United States of America

David C Davies