Other

Vlsi Technology, Inc.

Philips Electronics North America Corporation

Chapman, David C.

David C Chapman

Subhas Bothra

Michael N Misheloff

Wesley R Erck

Herve G Duprez

Harold J Levy

Peter Liebmann

An approach is provided for converting a polygon described as an ordered list of perimeter points into a set of connected quadrilaterals suitable for use in an advanced integrated circuit router. Edges are constructed between the points of the polygon. Then, one or more edges are selected as starting locations. Pairs of edges or portions of pairs of edges are matched to form sequences of quadrilaterals. Methods are provided to determine when edges should be split or skipped to ensure that all quadrilaterals are convex or meet other criteria. Other methods are provided to determine when the matching process should be terminated and restarted at another location. Finally, the sequences of quadrilaterals are joined together to form a data structure suitable for use within an integrated circuit router.

Method for reading polygon data into an integrated circuit router

A computer-implemented approach for routing an integrated circuit using non-orthogonal routing is accomplished during two phases: a global routing phase and a detailed routing phase. During global routing, routing indicators, in the form of hint polygons, are added to the integrated circuit layout and strategy lists, that include bias directions and straying limits, are generated for the new wires to be added. The hint polygons and strategy lists are used during detailed routing to aid in placing the new wires. If obstacle conflicts or insufficient space problems prevent the detailed routing of a new wire, then an obstacle resolution portion of global routing is used to resolve the obstacle conflict and/or provide additional space in the integrated circuit layout to route the new wires. Obstacle resolution includes, without limitation, moving or changing layout geometry, changing or add hint polygons, changing the routing strategy by changing the bias direction and/or adjusting straying limits, inserting one or more layer changes, instructing the detailed router to backup and insert a bend, ripping-up and rerouting one or more wires, or routing the wire from the destination connection point. Also, a tight routing approach may be employed to accommodate constructing routing paths in tight layout areas. Object specific design rule checks are employed to increase routing flexibility optimize routing performance. 'On-the-fly' design rule checks are performed on portions of routing paths as the routing paths are being constructed.

Approach for routing an integrated circuit

Disclosed is a method for checking integrated circuit layout design files. The method includes identifying a via geometry that is laid out on a via mask file. Identifying a metallization geometry that is laid out on a metallization mask file. Shifting the via geometry in a first orientation to produce a first shifted via geometry. Performing a logical AND between the first shifted via geometry and the metallization geometry. The method further includes determining whether the logical AND produces a value indicative of a sufficient overlap between the identified metallization geometry and the first shifted via geometry.

Methods and apparatus for design rule checking

An approach for representing polygons in an integrated circuit (IC) layout is provided. Polygons are represented by one or more wires, which in turn are each represented by one or more wire segments. Each wire segment is represented by a pair of directed line segments. A data structure hierarchy includes polygon data, wire data, wire segment data and branch data. The polygon data represents a set of IC devices to be represented in the IC layout. The wire data represents the wires that represent the polygons and specifies the associated wire segments and associated polygons. The wire segment data represents the wire segments and specifies the associated directed line segments for each wire segment that represent the wires and references the wire data. The branch data specifies connections between wires by specifying the connecting wire segments in the wires. A spacing check between a first polygon and a second polygon involves determining the canonical direction from the first polygon to the second polygon and testing the two closest faces between the polygons. To satisfy a spacing violation, an exclusion zone is constructed around the first polygon and the second polygon is moved a distance outside the exclusion zone which causes the minimum spacing required by a set of predetermined spacing criteria to be satisfied.

Polygon representation in an integrated circuit layout

In a computer implemented circuit simulator, a method is provided for measuring energy consumption of a circuit under test during a measurement interval. The method comprises a series of computer implemented steps. A supply voltage is applied to the circuit under test. A current flowing through the circuit under test is then measured. A mirror voltage, representative of the value of the current, is generated. A capacitor is charged, with a power parameter voltage equal to the product of the supply voltage and the mirror voltage, during the measurement interval. An accumulated voltage is measured across the capacitor, wherein the accumulated voltage is representative of energy consumed by the circuit under test.

Method of measuring energy consumption in a circuit simulator

A method for labelling polygons of a geometric layout which includes the steps of scanning a geometric layout during a first scan line pass to detect objects which form a polygon, processing the scan line at each occurrence of an event to detect the objects which contact the scan line, assigning temporary numbers and root designators to the objects which contact the scan line in accordance with a sorting criterion, updating the temporary numbers assigned to the objects to keep the temporary number associated with the earliest root designator of each separately detected polygon, and renaming each object which forms a part of the same polygon with a common label. The step of updating includes the steps of numbering each object in a polygon with a temporary number assigned to a root object of the polygon, and storing, in a sorted order, the root objects which lose their status as root objects during the step of updating.

Method for labelling polygons

An apparatus and a method for making a reticle mask is disclosed. A reticle mask is made by the double pass method wherein scribe lines are first drawn on the reticle mask. Thereafter, a product die pattern is made in the reticle mask by a plurality of times. A plurality of alignment marks are associated with each product die pattern. The plurality of alignment marks are all written in the scribe line region. Thus, any deviation of the relative position of the product die pattern to the scribe line may be quantified.

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Santa Clara, CA, United States of America

David C Chapman