Emc Corporation

Emc IP Holding Company LLC

David C Bisbee

Stephen Edward Strickland

Joseph P King

Ralph C Frangioso, Jr

John Blondin

Thomas Earl Linnell

Brian William Gallagher

Erik C Nelson

William R Tuccio

Edward J Claprood

Lawrence G Pignolet

Christopher J Mulvey

Scot C Tata

Enrico DiFabio

Thomas Delucia

A system board includes at least one microprocessor coupled to the system board. A VR module card includes a voltage regulator circuit, wherein the voltage regulator circuit is configured to provide electrical power to the at least one microprocessor. A circuit board region is configured to receive the VR module card.

Configurable system board

A system board includes at least one microprocessor coupled to the system board. A first circuit board region is populated with a first model voltage regulator circuit. The first model voltage regulator circuit is configured to provide electrical power to the at least one microprocessor. A second circuit board region is unpopulated and configured to receive a second model voltage regulator circuit.

A system for generating and monitoring voltages on a variety of different components on a common printed circuit board. The system includes a programmable controller, a plurality of DC/DC converters for producing voltages for the devices and a plurality of voltage regulators for produced voltages for a plurality of CPUs on the board, such CPU voltages being produced in accordance with VIDs provided to the regulator by the CPU. The programmable controller: establishes a set point voltage for such one of the DC/DC converters; sequentially monitors the produced voltages produced, monitors voltages produced by the regulators for the CPUs by comparing the VIDs to the voltages produced by the regulators, and if during the sequencing any one of the converters is determined by the programmable controller as producing an improper voltage or if the any one of the regulators fails top produce the voltage indicated by the VIDs, disables the board.

System for generating and monitoring voltages generated for a variety of different components on a common printed circuit board

A data storage interface for coupling data between processors and a bank of disk. The interface includes a plurality of first directors coupled to the processors and a plurality of second directors coupled to the bank of disk drives. A cache memory is coupled between the plurality of first directors and the plurality of second directors. The interface includes a pair of independent power busses. At least one of the first or second directors is coupled to the pair of independent power busses. One portion of the disk drives in the bank is connected to only a first one of the pair of power buses and a different portion of the disk drives is connected to only the other one of the pair of power buses. A power circuit includes a pair of input terminals, each one being electrically connected to a corresponding one of the pair of independent power busses. The circuit includes an output terminal. A pair of switching transistor sections is provided. The transistor switching sections is serially connected between a corresponding one of the pair of input terminals and the output terminal. A logic network is provided for operating the switching sections to prevent current passing into one of the pair of input terminals from one of the power busses from passing into the other one of the power buses. The logic section operates the switching sections to prevent current from one of the pair of power buses to the one of the input terminals connected thereto from exceeding a predetermined value, and operates the switching sections to prevent a difference between a voltage at one of the input terminals and a voltage at the other one of the input terminals from exceeding a predetermined value.

Dual power bus data storage system

A data storage system wherein a host computer is coupled to a bank of disk drives through a system interface. The interface has a memory with a high address memory section and a low address memory section. A plurality of directors control data transfer between the host computer and the bank of disk drives as such data passes through the memory. A pair of high address busses electrically is connected to the high address memory and a pair of low address busses is electrically connected to the low address memory. Each one of the directors is electrically connected to one of the pair of high address busses and one of the pair of low address busses. A front-end portion of the directors is electrically connected to the host computer and a rear-end portion of the directors is electrically connected to the bank of disk drives. The bank of disk drives has a plurality of sets of electrically connected disk drives, each one of the sets being connected to a corresponding one of the input/output interfaces of a corresponding one of the rear-end directors through the adapter card connected to such corresponding one of the rear-end directors and, through the printed circuit board, to the adapter card in the another one of the electrical connectors and to the input/output interface of the rear-end director in such other one of the electrical connectors. Each pair of a plurality of bus arbiters is electrically connected to ends of a corresponding one of the busses. One of the arbiters is a master arbiter and the other a slave arbiter. A pair of reference voltage generator is also connected to ends of each bus.

Data storage system having a host computer coupled to bank of disk drives through interface comprising plurality of directors, busses, and reference voltage generators

A computer storage system includes director boards which control transfer of data to and between a host computer, a system cache memory and a disk array. The directors are provided with features which enhance system performance and reliability. A hardware emulation controller permits a high performance processor to be used with existing system circuitry. A control store memory is organized with primary and secondary data areas and primary and secondary parity areas. Data is written to both the primary and secondary areas. A read request accesses data in the primary area and performs a retry in the secondary area in the event of a parity error. A power supply system includes on-board marginable power supplies to facilitate testing and power-up by-pass circuits for protection of sensitive circuitry. A system clock configuration employs primary and secondary clocks to ensure redundancy of synchronized timekeeping.

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Princeton, MA, United States of America

David C Bisbee