Motorola Corporation

Nxp USA, Inc.

David C Babin

John D Hatchett

Edward A Kuligowski

Embodiments are provided for a quaternary decoder that includes a plurality of decoder circuits, each decoder circuit coupled to a respective input line of a plurality of quaternary interface lines and to a respective pair of binary output lines; and a control logic circuit having a plurality of control signal lines coupled to each of the plurality of decoder circuits, the control logic circuit configured to: output a first sequence of logic levels, and output a second sequence of logic levels after the first sequence is complete; wherein at a time after the second sequence is complete, each decoder circuit is configured to output a pair of binary data values that correspond to a quaternary state of the respective input line, the quaternary state being one of four quaternary states including a logic high state, a logic low state, a floating state, and a tie-back state.

Quaternary decoder

A method and apparatus for providing serially shifted data to a plurality of registers (51 through 56) begins by providing an enable signal (14). A first time portion of the enable signal (14) is either asserted or pulsed in order to provide a bank select control signal to a bank select circuit (74). After providing the bank select information, the enable (14) is activated in order to enable the storage of serial input data within a register (40). While data is being provided via a data input (16) to the register (40), a monitoring circuit (72) is recording the number of clocks (12) required to provide the entire sequence data into the register (40). A combination of the decoding information provided by the bank select circuit (74) and the monitoring circuit (72) allows one of a plurality of registers to be written with the data from register (40) even when the registers (51 through 56) are of a same size.

Serial interface with register selection which uses clock counting, chip

A cascadable peripheral (10) has at least two registers (51, 52, 53) of different sizes. Input data is shifted serially through a shift register (40) synchronously with a clock signal. A serial output of the shift register (40) is provided to a data output terminal (18) of the peripheral (10) for cascading. A counter (20) increments a state in response to the clock signal. A decode portion (30, 31, 32, 33, 35) activates one of a group of load signals, corresponding to one of the registers (51, 52, 53), in response to a state of the counter (20), when an enable signal becomes inactive. The active load signal causes the corresponding register to load a value presented from a parallel data output of the shift register (40). The counter (20) is reset in response to either the enable signal becoming inactive or the counter (20) reaching a maximum count corresponding to a size of the shift register (40).

Cascadable peripheral data interface including a shift register,

An integrated circuit with a serial data port includes a counter for counting clock pulses and generating a binary signal, a decoder for converting the binary signal to a load signal to access an appropriately sized register, a serial-in, parallel-out shift register for receiving serial data and outputting the data in parallel, and a plurality of registers. The registers receive the load signal from the decoder and have a multi-bit data input for receiving the parallel data from the shift register. The circuit can access an appropriately sized register by using the counter and the decoder instead of address bits, and therefore reduce the total bit stream length. The circuit can randomly select any register out of several registers having different bit lengths.

Serial data circuit with randomly-accessed registers of different bit

A synthesizer is placed in standby mode when a standby portion of a control register is set. Once standby is activated, any detectors and counters are inhibited. The inputs and outputs are reconfigured so as to minimize current drain and to stabilize the VCO control voltage. Recovery from standby is accomplished in two phases. The first phase is started by the receipt of a terminate standby signal. This enables the inputs and starts the counters. The second phase is activated when a signal is received from a feedback counter indicating it has completed a cycle. This causes the preset data to be loaded into the reference counter. The counters are then synchronized; the detector is initialized; and the detector output is enabled. The device also controls an output lock detector and reference frequency signal during the standby mode. The system is also compatible with variable modulus prescalers.

Standby system for a frequency synthesizer

A display driver system having a plurality of series-coupled display drivers which are synchronized by using the same conductor between adjacent display drivers for communicating display data and synchronization control signals. The display driver serially receives display information at a predetermined clock rate. One of the display drivers becomes a master over the remaining display drivers and provides synchronization data for the system. Each display driver selectively outputs either display information or control information at a single output terminal.

Synchronization method and circuit for display drivers

A PLL frequency synthesizer IC chip having a sample frequency input terminal, data and address lines and a plurality of different output devices, and a mode control circuit for turning off any selected ones of the different output devices. The mode control circuit comprises a plurality of inputs connected to at least one of the data and address lines for determining different modes of operation, and a plurality of outputs connected to the plurality of different output devices for selecting ones of the plurality of different output devices to allow outputting therefrom and shutting off outputs from all of the remaining different output devices, based on the determined mode of operation.

PLL frequency synthesizer output control circuit

A phase locked loop for providing a programmable frequency output signal with reduced phase-frequency lock time. A phase detector detects a phase difference between a reference frequency divided by a first number, and a frequency of the output signal divided by a second number. First and second counters receive the first and the second input numbers to divide a respective frequency. Whenever an input number is loaded, a load signal resets the phase detector and causes each counter to be loaded, which reduces the lock time of the loop.

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Austin, TX, United States of America

David C Babin