Motorola Corporation

Freescale Semiconductor,inc.

Stmicroelectronics (crolles 2) Sas

David Burnett

James R Pfiester

James D Hayden

Wei-Hua Liu

Richard Ferrant

Prashant U Kenkare

Craig T Swift

Shayan Zhang

Michael D Snyder

Andrew Christopher Russell

Bradford Lawrence Hunter

Kuo-Tung Chang

Troy L Cooper

Pierre Malinge

Chung-You Hu

Franck Genevaux

Gerald Gouya

Ravindraj Ramaraju

A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.

Semiconductor array including a matrix of cells and a method of making a semiconductor array having a matrix of cells

A device is disclosed having a low-voltage memory device. The device includes a first memory having a first memory topology and a second memory having a second memory topology, with both memories located in an integrated circuit. The first memory is a relatively high-density memory device, capable of storing large amounts of data relative to the second memory. The second memory is a low-voltage memory device capable of being accessed at low-voltages relative to the voltage at which the first memory can be accessed. Accordingly, the second memory is accessible when the integrated circuit is placed in a low-voltage mode of operation, which may represent a data retention state (sleep state) for the first memory or other portions of the integrated circuit. Thus, the device is able to store large amounts of data in the high density memory in a normal or active mode of operation, and also have access to the low-voltage memory during the low-voltage mode of operation.

Low voltage memory device and method thereof

A semiconductor device includes a non-volatile memory, such as an electrically erasable programmable read only memory (EEPROM) array of memory cells. The memory is arranged as an array of cells in rows and columns. P-well regions of the array are spaced apart and electrically isolated by shallow trench features. The cells of each column are positioned within a respective isolated p-well region. Control gates of sequentially corresponding memory cells in columns of the array are electrically coupled by common wordlines. Bitlines electrically couple drain regions of each memory cell in the respective columns of the memory cell array. Source lines electrically couple source regions of each memory cell in the respective columns of the array. The source lines and at least one memory cell in each column of the array are electrically coupled to the p-well region corresponding to the column of the source line and cell. Each column of the array is therefore located within an isolated well, common to the cells in the column but isolated from other wells of other columns. The array is programmed by pulsing potentials as to each column, with isolation of results for each column.

Non-volatile memory, method of manufacture, and method of programming

A semiconductor device (150) is formed having a first conductive member (64) overlying a field isolation region (36) that is typically less than two microns wide. Typically, the field isolation region (36) is relatively thinner compared to wider field isolation regions. The first conductive member (64) lies between the field isolation region (36) and a second conductive member (80) to shield the substrate (20). The shielding helps to increase the field threshold voltage of the field device. The invention is particularly useful in double polysilicon process flow used in forming devices operating at a potential higher than V.sub.DD. Examples of these devices include nonvolatile memories and microcontrollers having nonvolatile memory arrays.

Process for forming a semiconductor device having a conductive member

A method is provided for the formation of ultra-shallow boron doped regions in a semiconductor device. In one embodiment of the invention an N-type semiconductor substrate (15) is provided having a first P-type region formed therein. A dielectric layer (16) is formed on the substrate surface and a material layer (17) doped with fluorinated boron is formed on the dielectric layer (16). A second P-type region (22), characterized by a high dopant concentration at the substrate surface and a uniform junction profile, is formed in the substrate adjacent to the first P-type region by diffusing boron atoms from the material layer (17) through the dielectric layer (16) and into the substrate (15). The second P-type region (22) has a very shallow junction depth which is closer to the substrate surface than the first P-type region.

Method for fabricating a semiconductor device having a shallow doped

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David Burnett