Xilinx, Inc.

Uber Technologies, Inc.

Altera Corporation

David Bruce Parlour

Jorn W Janneck

Ian D Miller

Paul R Schumacher

F Erich Goetting

Stephen M Trimberger

Carlos Vallespi-Gonzalez

George Totolos, Jr

Pradip Jha

Joshua Oren Silberman

Daniel Leland Strother

Michael Alan Baxter

Christopher D Ebeling

John E Mahoney

Richard S Ballantyne

Roger D Carpenter

Edel M Young

Michael Glenn Wrighton

Image processing systems can include one or more cameras configured to obtain image data, one or more memory devices configured to store a classification model that classifies image features within the image data as including or not including detected objects, and a field programmable gate array (FPGA) device coupled to the one or more cameras. The FPGA device is configured to implement one or more image processing pipelines for image transformation and object detection. The one or more image processing pipelines can generate a multi-scale image pyramid of multiple image samples having different scaling factors, identify and aggregate features within one or more of the multiple image samples having different scaling factors, access the classification model, provide the features as input to the classification model, and receive an output indicative of objects detected within the image data.

FPGA device for image classification

A structure for a parallel cyclic redundancy check (CRC) structure in which the number of cycles in the loopback can be arbitrarily extended is provided. The parallel CRC structure includes a reweighting module in the feedback loop that is pipelined into multiple stages. The parallel CRC structure also includes multiple feed forward reweighting modules that correspond to the multiple pipeline stages in the feedback loop. The reweighting module in the feedback loop accumulates and reweights the contribution of all symbols in the message, while the N reweighting modules in the N parallel feed-forward paths provide the contributions of the symbols that are 'in-flight' within the feedback loop to the final CRC checksum.

CRC circuits with extended cycles

A method of generating data for estimating resource requirements for a circuit design is disclosed. The method comprises identifying a plurality of intermediate circuit modules of netlists for circuit designs; elaborating each intermediate circuit module of the plurality of intermediate circuit modules according to an associated plurality of parameter sets; generating an estimate of resources for each intermediate circuit module and parameter set of the associated plurality of parameter sets; and storing the estimates of resources for the intermediate circuit modules.

Method of generating data for estimating resource requirements for a circuit design

Automatic queue sizing for data flow applications for an integrated circuit is described. Queue sizes for queues of a dataflow network are initialized to a set of first sizes for running as distributed actors without having to have centralized control. If it is determined there is a deadlock, causes for the dataflow network being deadlocked are analyzed with a controller coupled thereto to select a first actor thereof. The first actor of the dataflow network is selected as being in a stalled write phase state. Queue size is incremented for at least one queue of the queues to unlock the first actor from the stalled write phase state. The running, the determining, the analyzing, and the incrementing are iteratively repeated to provide a second set of sizes for the queue sizes sufficient to reduce likelihood of deadlock of the data flow network.

Automatic queue sizing for dataflow applications

In one embodiment, a concurrent processing system is disclosed. For example, in one embodiment of the present invention, a concurrent processing system, comprises a first processing element comprising a first monitor module, a second processing element in communication with the first processing element, the second processing element comprising a second monitor module, and a first system monitor for receiving a notification from at least one of: the first processing element, or the second processing element, wherein the notification indicates an event detected by one of the first monitor module, or the second monitor module.

Method and apparatus for processing an event notification in a concurrent processing system

An asynchronous communication network in an integrated circuit is described. The asynchronous communication network comprises a plurality of circuit elements enabling the transmission of tokens, each circuit element having a component interface comprising: a routing network coupled to a first adjacent circuit element of the plurality of circuit elements; and a control circuit coupled to the routing network, the control circuit having a first input coupled to receive a first command requesting a detection of a token received at a second input of the control circuit, and a first acknowledgement output coupling a first acknowledgement signal indicating whether the first command is received at the first input. Methods of enabling asynchronous communication in an integrated circuit are also disclosed.

Asynchronous communication network and methods of enabling the asynchronous communication of data in an integrated circuit

Method and apparatus for generating an implementation of a program language circuit description for a programmable logic device (PLD) is described. In one example, the program language circuit description is analyzed to identify constructs indicative of dynamic function re-assignment. A hardware description of the program language circuit description is generated. The hardware description includes a plurality of implementations responsive to the identified constructs. Physical implementation data is generated from the hardware description. The physical implementation includes a plurality of partial configurations for the PLD based on the respective plurality of implementations in the hardware description.

Method and apparatus for supporting run-time reconfiguration in a programmable logic integrated circuit

A method of evaluating an architecture for an integrated circuit device is disclosed. The method comprises generating a library of primitives for a predetermined architecture; transforming an original dataflow program into an intermediate format; transforming the intermediate format to a dataflow program defined in terms of the predefined library of primitives; and generating an implementation profile comprising information related to an implementation of the original dataflow program in an integrated circuit having the predetermined architecture. A method of evaluating an architecture for an integrated circuit device is also disclosed.

Method of evaluating an architecture for an integrated circuit device

Disclosure is made of approaches for mapping an electronic design specification to an implementation. In one approach, quality metrics are associated with functional units of the design, and the functional units are mapped to respective initial implementations. For each functional unit a respective quality indicator is determined based on the mapping. The quality indicator specifies a degree to which the functional unit achieves the associated quality metric. At least one of the functional units is selected for remapping based on the quality indicator of that functional unit or the quality indicator of another functional unit. An alternative implementation to the initial implementation is selected for each selected functional unit to improve the quality indicator. The selected functional unit is remapped to the selected alternative implementation.

Automated method of architecture mapping selection from constrained high level language description via element characterization

A method of estimating resource requirements for a circuit design is disclosed. The method comprises identifying intermediate circuit modules of a netlist associated with the circuit design; accessing a library of resource requirements for intermediate circuit modules of netlists for circuit designs; selecting intermediate circuit modules of the library according to predetermined parameters for the circuit design; and generating an estimate of resource requirements for the circuit design based upon resource requirements of the selected intermediate circuit modules.

Method of estimating resource requirements for a circuit design

Dataflow control for an application with timing parameters, including interfacing temporal and non-temporal domains, is described. The domains receive input data to a first dataflow network block, which is processed for untimed output of first tokens. The first tokens are obtained by a memory interface for timed writing of data portions of the first tokens to data storage and for timed reading of the data portions therefrom. Sending of the data portions read to a first queue of a first controller block is untimed, and the data portions are output by the first controller block with physical timing parameters. Second tokens are generated by the first controller block responsive to the physical timing parameters. The second tokens are fed back to a second queue of the first dataflow network block to control rate of generation of the first tokens by the first dataflow network block.

Dataflow control for application with timing parameters

Method and apparatus for processing a dataflow description of a digital processing system is described. In one example, a model of the dataflow description is simulated. Computational steps performed during the simulation and actual dependencies among the computational steps resulting from the simulation are identified. Causation trace data is generated in response to the step of recording. The causation trace data may then be analyzed using one or more analyses to produce quantitative data that characterizes the dataflow description.

Method and apparatus for processing a dataflow description of a digital processing system

Method and apparatus for implementing a program language description of a circuit design for an integrated circuit is described. In one example, a program is specified using a concurrent programming language. The program includes programming constructs that define a plurality of processes and a plurality of communication channels. A hierarchy of elements that classify the programming constructs of the program are generated to produce a transformed representation. A hardware description language (HDL) representation of the circuit design is generated from the transformed representation by translating the hierarchy of elements to a hierarchy of HDL constructs that implements the plurality of processes and the plurality of communication channels in hardware.

Method and apparatus for implementing a program language description of a circuit design for an integrated circuit

Method and system for dynamically adjusting performance of circuitry blocks are described. A first circuit domain is coupled to an interim storage device. The first circuit domain includes a first level shifter coupled to an input of a first circuitry block and a second level shifter coupled to an output of the first circuitry block. The second level shifter is coupled between the output of the first circuitry block and an input of the interim storage device. A controller is coupled to the first circuit domain for adjustment of a first operating voltage of the first circuit domain.

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Pittsburgh, PA, United States of America

David Bruce Parlour