Nvidia Corporation

Newisys, Inc.

International Business Machines Corporation

Tesla, Inc.

Other

Sanmina Corporation

Memory Integrity, LLC

David Brian Glasco

Rajesh Kota

Patrick Rene Marchand

Peter B Holmqvist

James P Roberts

George R Lynch

Gary Dale Carpenter

Guru Prasadh

Carl Zeitler

John Stephen Montrym

Mark Edward Dean

Karan Mehra

Lingfeng Yuan

John H Edmondson

Daniel William Bailey

Richard R Oehler

Shashank Nemawarkar

Patryk Kaminski

Dane Mrazek

Richard Nicholas Iachetta, Jr

Thaddeus Fortenberry

Steven E Molnar

Ronald Lynn Rockhold

Yin Fung Tang

Charles Edward Watson, Jr

Ramakrishnan Rajamony

Emmett Michael Kilgariff

Cass Watson Everitt

Bishop Chapman Brock

Sridhar Valluru

Yongxiang Liu

Freeman Leigh Rawson, Iii

Jonah Matthew Alben

Brian K Langendorf

Samuel Hammond Duncan

Elmootazbellah Nabil Elnozahy

Sean Jeffrey Treichler

Michael Brian Cox

Atchyuth Gorti

Samuel Douglas Crowder

Eli Chiprout

William G Kulpa

Shashank Newawarker

Les Record

John Peyton Bannister

James Stephen Fields, Jr

James Leroy Deming

William P Newhall, Jr

John M Danskin

David Kirk McAllister

Eric Christopher Morton

Dennis K Ma

Wei-Je Robert Huang

Colyn Scott Case

James Lyle Peterson

Robert C Keller

Yoanna Baumgartner

Ravi Kiran Manyam

Anna Elman

David Edrich

Scott S Diesing

Atul Kalambur

Philippe Louis deBacker

Yin Fung (David) Tang

Adnan Khaleel

A vehicular autonomous driving system includes a fault prediction unit, including a processor and memory, configured to predict a potential future fault condition by: monitoring performance data associated with the plurality of autonomous driving components; comparing the performance data associated with the plurality of autonomous driving components to a plurality of performance thresholds; and determining the potential future fault condition for one of the plurality of autonomous driving components, when the performance data associated with the one of the plurality of autonomous driving components compare unfavorably to corresponding one of the plurality of performance thresholds.

Autonomous driving system component fault prediction

A parallel processing system includes at least three parallel processors, state monitoring circuitry, and state reload circuitry. The state monitoring circuitry couples to the at least three parallel processors and is configured to monitor runtime states of the at least three parallel processors and identify a first processor of the at least three parallel processors having at least one runtime state error. The state reload circuitry couples to the at least three parallel processors and is configured to select a second processor of the at least three parallel processors for state reload, access a runtime state of the second processor, and load the runtime state of the second processor into the first processor. Monitoring and reload may be performed only on sub-systems of the at least three parallel processors. During reload, clocks and supply voltages of the processors may be altered. The state reload may relate to sub-systems.

Parallel processing system runtime state reload

An autonomous driving controller includes a plurality of parallel processors operating on common input data. Each of the plurality of parallel processors includes a general processor, a security processor subsystem (SCS), and a safety subsystem (SMS). The general processors, the SCSs, and the SMSs of the plurality of parallel processors are configured to first, boot the plurality of SCSs from ROM second, boot the plurality of SMSs of the plurality of parallel processors from RAM or ROM, and, third, boot the plurality of general processors of the plurality of parallel processors from RAM. Between booting of the SCSs and the SMSs, at least one of the plurality of SCSs may load SMS boot code into the RAM that is dedicated to the plurality of SMSs.

Autonomous driving controller parallel processor boot order

An example SoC includes a plurality of processing systems supporting respective Quality of Service (QoS) rules, channel circuitry that is configured to service communications for the plurality of processing systems and that includes a QoS manager. The QoS manager determines that a first processing system of the plurality of processing systems that operates according to first QoS rules desires to send a communication with a first QoS selection of the first QoS rules to a second processing system that operates according to second QoS rules, determines available communication receipt resources of the second processing system of the plurality of processing systems, the second processing system supporting second QoS rules, determines a communication resources allocation for the second processing system based upon the first QoS rules, the second QoS rules, and the first QoS selection, and directs the second processing system to operate according to the communication resource allocation.

QoS manager for system on a chip communications

An autonomous driving controller includes a plurality of parallel processors operating on common input data received from the plurality of autonomous driving sensors. Each of the plurality of parallel processors includes communication circuitry, a general processor, a security processor subsystem (SCS), and a safety subsystem (SMS). The communication circuitry supports communications between the plurality of parallel processors, including inter-processor communications between the general processors of the plurality of parallel processors, communications between the SCSs of the plurality of parallel processors using SCS cryptography, and communications between the SMSs of the plurality of parallel processors using SMS cryptography, the SMS cryptography differing from the SCS cryptography. The SCS and/or the SMS may each include dedicated hardware and/or memory to support the communications.

Autonomous driving controller encrypted communications

A vehicular autonomous driving system includes a fault prediction unit, including a processor and memory, configured to predict a potential future fault condition by: monitoring performance data associated with the plurality of autonomous driving components; comparing the performance data associated with the plurality of autonomous driving components to a plurality of performance thresholds; and determining the potential future fault condition for one of the plurality of autonomous driving components, when the performance data associated with the one of the plurality of autonomous driving components compares unfavorably to a corresponding one of the plurality of performance thresholds.

A parallel processing system includes at least three processors operating in parallel, state monitoring circuitry, and state reload circuitry. The state monitoring circuitry couples to the at least three parallel processors and is configured to monitor runtime states of the at least three parallel processors and identify a first processor of the at least three parallel processors having at least one runtime state error. The state reload circuitry couples to the at least three parallel processors and is configured to select a second processor of the at least three parallel processors for state reload, access a runtime state of the second processor, and load the runtime state of the second processor into the first processor. Monitoring and reload may be performed only on sub-systems of the at least three parallel processors. During reload, clocks and supply voltages of the processors may be altered. The state reload may relate to sub-systems.

A System on a Chip (SoC) includes a plurality of general purpose processors, a plurality of application specific processors, a plurality of SoC support processing components, a security processing subsystem (SCS), a general access Network on a Chip (NoC) coupled to and servicing communications between the plurality of general purpose processors and the plurality of SoC support components, and a proprietary access NoC coupled to and servicing communications for the plurality of application specific processors and the SCS. The SoC may further include a safety processor subsystem (SMS) coupled to the proprietary access NoC, wherein the proprietary access NoC further services communications for the SMS and isolates communications of the SMS from communications of the plurality of general purpose processors. The general access NoC and the proprietary access NoC isolate communications of the SCS and the SMS from communications of the plurality of general purpose processors.

Isolation of subsystems on a system on a chip

QOS manager for system on a chip communications

One embodiment of the present invention sets forth a technique for increasing available storage space within compressed blocks of memory attached to data processing chips, without requiring a proportional increase in on-chip compression status bits. A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing store residing in a reserved region of attached memory provides storage for a complete set of compression status bits used to represent compression status of an arbitrarily large number of blocks residing in attached memory. Physical address remapping ('swizzling') used to distribute memory access patterns over a plurality of physical memory devices is partially replicated by the compression status bit cache to efficiently integrate allocation and access of the backing store data with other user data.

Compression status bit cache and backing store

A multi-processor computer system is described in which transaction processing is distributed among multiple protocol engines. The system includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.

Multiple protocol engine transaction processing

One embodiment of the invention sets forth a control crossbar unit that is designed to transmit control information from control information generators to destination components within the computer system. The control information may belong to various traffic paradigms, such as short-latency data traffic, narrow-width data traffic or broadcast data traffic. The physical connections within the control crossbar unit are categorized based on the different types of control information being transmitted through the control crossbar unit. The physical connections belong to the following categories: one-to-one (OTO) connections, one-to-many (OTM) connections, valid-to-one (VTO) connections, valid-to-many (VTM) connections wire-to-one (WTO) connections and wire-to-many (WTM) connections.

Mitigating main crossbar load using dedicated connections for certain traffic types

Growing community of inventors

Austin, TX, United States of America

David Brian Glasco