National Semiconductor Corporation

Texas Instruments Corporation

David Brian Barkin

Ira Oaktree Wygant

Robert Callaghan Taft

Heinz Werker

Pier Francese

Joshua Posamentier

Bumha Lee

Matthew Louis Courcy

Sing W Chin

James Brinkhurst

A flow meter system includes a first ultrasonic transducer array to be flush-mounted to a pipe. The system also includes a second ultrasonic transducer array to be flush-mounted to the pipe. The system further includes a controller coupled to the first and second ultrasonic transducer arrays and configured to cause bidirectional beam steering between the first and second ultrasonic transducer arrays.

Flush mounted ultrasonic transducer arrays for flow measurement

A micromachined ultrasonic transducer (MUT) circuit, which has a MUT with a MUT membrane that can vibrate back and forth to transmit an ultrasonic wave, electrically controls the movement of the MUT membrane by controllably transferring energy to the MUT membrane, thereby allowing the MUT membrane to transmit substantially any desired ultrasonic wave.

MUT circuit with an electrically controllable membrane

A method of operating a line imaging device including receiving a first clock signal indicative of a system timing signal in the line imaging device, generating a second clock signal based on the first clock signal and being unmodulated where the second clock signal being used for driving the imager timing, data sampling and digitizing operations of the line imaging device, and generating a third clock signal based on the first clock signal and being modulated using a spreading waveform where the third clock signal being a spread spectrum clock signal and being used to drive the data transfer operation of the line imaging device.

Mixed domain spread spectrum clocking for use in imaging systems for maximum imaging quality and optimized EMI performance

A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.

Continuous synchronization for multiple ADCs

A gain-boosted telescopic amplifier () includes clamping circuits for the bias devices to ensure fast over-voltage recovery. In one embodiment, the gain-boosted telescopic amplifier includes an input pair of NMOS transistors (M, M), a pair of NMOS gain-boosted cascode transistors (M, M) and a pair of PMOS gain-boosted cascode transistors (M, M). The amplifier includes first and second clamping circuits driving the gate terminals of the pair of PMOS cascode transistors, respectively. The clamping circuits limit the gate voltage of the PMOS cascode transistors to be within a threshold voltage from the desired bias voltage. Each clamping circuit can include only a pull-down device, a pull-up device or both. In another embodiment, the amplifier includes clamping circuits driving the gate terminals of the pair of NMOS cascode transistors for limiting the gate voltage of the NMOS cascode transistors to be within a threshold voltage of the desired bias voltage.

Growing community of inventors

San Francisco, CA, United States of America

David Brian Barkin