Texas Instruments Corporation

David Brian Aldrich

Patricia Beauregard Smith

Kenneth D Brennan

Guoqiang Xing

Douglas A Prinslow

Eden M Zielinski

Peter S McAnally

Andrew Marshall

Antonio L P Rotondaro

Stephen W Russell

Eric C Williams

Systems and methods are provided for contactless testing of a wafer containing at least one integrated circuit. A test component responds to a supply voltage to indicate at least one property of the wafer. A voltage source wirelessly receives power from an external source and produces the supply voltage. A reference generator generates a reference voltage, having a known magnitude, from the supply voltage. A voltage evaluation component modifies the response of the test component as to represent a magnitude of the supply voltage.

Contactless testing of wafer characteristics

An inductor integrated in a semiconductor device comprises a first and second lower electrical trace, an upper electrical trace, aligned at a first end with a first end of the first lower electrical trace and at a second end with a second end of the second lower electrical trace, a first via intercoupling the first end of the upper electrical trace with the first end of the first lower electrical trace, and a second via intercoupling the second end of the upper electrical trace with the second end of the second lower electrical trace.

System for integrating a toroidal inductor in a semiconductor device

Another embodiment of the instant invention is a method of fabricating a conductive interconnect for providing an electrical connection between a first conductor and a second conductor for an electrical device formed in a semiconductor substrate, the method comprising the steps of: forming a dielectric layer (layerof FIG.) on the first conductor (conductorof FIG.), the dielectric layer having at least one opening which exposes the first conductor; forming a layer of an oxygen-sensitive material (layerof FIG.) on the dielectric layer, the oxygen-sensitive material substantially filling the opening in the dielectric layer and for providing an electrical contact to the first conductor; forming a photoresist layer on the oxygen-sensitive material, the photoresist layer having a pattern so as to expose portions of the oxygen-sensitive material; removing the exposed portions of the oxygen-sensitive material on the dielectric material, the removal step causing a residue to be formed on exposed surfaces of the remaining portions of the oxygen-sensitive material; and removing the photoresist layer by subjecting the photoresist layer with a hydrogen-containing gas incorporated into a plasma.

Hydrogen plasma photoresist strip and polymeric residue cleanup process for oxygen-sensitive materials

An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layerof FIG.) over the substrate; forming a photoresist layer (layerof FIG.) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium. The gas which includes hydrogen or deuterium is, preferably, comprised of a gas selected from the group consisting of: NH, NH, HS, CH, and deuterated forms of these gases, and may, additionally, include a forming gas. The forming gas is, preferably, comprised of a gas consisting of: argon, nitrogen, and any other inert gas.

Method for photoresist strip, sidewall polymer removal and passivation for aluminum metallization

A cleanup process that uses a dilute fluorine in oxygen chemistry in a downstream plasma tool to remove organic and inorganic polymeric residues ( ).

Dry process for post oxide etch residue removal

An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer of FIG. ) over the substrate; forming a photoresist layer (layer of FIG. ) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium. The gas which includes hydrogen or deuterium is, preferably, comprised of a gas selected from the group consisting of: NH , N H , H S, CH , and deuterated forms of these gases, and may, additionally, include a forming gas. The forming gas is, preferably, comprised of a gas consisting of: argon, nitrogen, and any other inert gas.

A versatile system for reducing electromagnetic interference resulting from an inductor ( ) formed within an integrated circuit is disclosed, including an inductor layer ( ) having conductive elements ( ) about its perimeter, first ( ) and second ( ) isolation layers disposed upon on opposite sides of the inductor layer and having conductive elements ( ) about their perimeters, and first ( ) and second ( ) shield layers surrounding the first and second isolation layers, respectively, and coupled together by the conductive elements ( ) of the isolation and inductor layers.

Versatile system for integrated circuit containing shielded inductor

A structure and method to direct the via,etch to the top of the interconnect,by using a sidewall layer,preferably. TiN, and thus preventing the etching down the side of the interconnect,and exposure of materials residing between the interconnects

Sidewalls for guiding the via etch

A structure and method to direct the via 270 etch to the top of the interconnect 210, by using a sidewall layer 240, preferably TiN, and thus preventing the etching down the side of the interconnect 210 and exposure of materials residing between the interconnects 210.

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Allen, TX, United States of America

David Brian Aldrich