Maxim Integrated Products, Inc.

Intersil Corporation

David Bingham

Charles M Allen

Roger W Fuller

Pirooz Parvarandeh

Sui Ping Shieh

Peter D Bradshaw

Lee L Evans

Dane R Snow

Andrew M Wolff

Jules C Farago

An interface output stage includes a pull-up circuit and a pull-down circuit connected to a positive power supply signal line having a first voltage, an output signal line having an output voltage and a negative power supply signal line having a second voltage. The pull-up circuit includes a single output transistor and a body snatcher circuit, both interconnected between the positive power supply signal line and the output signal line. The body snatcher circuit ties the bodies of the output transistor and the transistors forming the body snatcher circuit to either the first voltage or the output voltage. The pull-down circuit is designed generally similar to the pull-up circuit to tie bodies of its transistors to either the output voltage or the second voltage.

Single output transistor output stage for interface applications

A substrate clamp for non-isolated integrated circuits is disclosed. The substrate clamp comprises a circuit that controls the voltage on a substrate so that the substrate is connected to a specific node if the parasitic PN diodes at all the circuit nodes are not forward biased. If a specific node is then forced with an applied voltage to forward bias, the substrate is disconnected from its original node and maintains itself at a forward biased diode voltage drop away from the powered node. Various embodiments are disclosed. In one embodiment of the invention, a set of bipolar transistors which utilize the substrate as a common base, is implemented. The emitters of these transistors are connected to a set of nodes which may be driven to voltages outside the range between that provided by the power supply and ground, or any other pair of applied voltages. The collectors of these bipolar transistors are connected together. When any or all of the bipolar transistors are turned on, the substrate is disconnected from the power supply terminal and is forced to a VBE or diode drop away from the emitter of the turned-on transistor. When the node returns to a voltage within the range of the power supply, the substrate is reconnected to the original power supply node.

Substrate clamp for non-isolated integrated circuits

A voltage overshoot limiter having a detector circuit that looks at the node at which the undesirable overshoot would occur and provides a signal that is proportional to the unipolar rate of change of voltage at the node. This output is fed back to the first stage of the control circuit, error amplifier, etc. in such a manner as to reduce the rate of change of the circuit's nodal voltages to less than their slewing rates. By modifying the value of the detector's output for a given detected slew rate at the node, it is possible to reduce both its overshoot significantly and to reduce its unipolar rate of voltage change. The invention is described as being unipolar, that is, responding to rates of change of voltages which are either positive or negative, though bipolar implementations may be realized.

Voltage overshoot limiter

A reverse current limited circuit configured to provide a reverse current limited low dropout voltage output. The reverse current limited circuit, coupled between a pair of terminals, comprises (i) a MOS pass transistor coupled in series between the first and second terminals, (ii) connection circuitry to connect the substrate of the MOS pass transistor to either one of the pair of terminals based on the relative magnitudes of the voltages measured on the pair of terminals, (iii) activation circuitry for turning on and off the MOS pass transistor based on the relative magnitudes of the voltages measured on the pair of terminals and (iv) comparison circuitry used to compare the voltages of the pair of terminals and to control the activation circuitry and the connection circuitry in response to the comparison made.

Reverse current prevention method and apparatus and reverse current

A current limited low dropout voltage circuit for coupling between first and second power supply terminals and an output terminal for providing a current limited low dropout voltage output having a MOS pass transistor coupled in series between the first power supply terminal and the output terminal, a drive circuit coupled to the gate of the MOS pass transistor, circuitry for limiting the gate-source voltage of the MOS pass transistor to limit the maximum current therethrough to a first maximum current level when the voltage between the second power supply terminal and the output terminal is less than a predetermined value, and circuitry for limiting the gate-source voltage of the MOS pass transistor to limit the maximum current therethrough to a second maximum current level when the source to drain voltage of the MOS pass transistor is greater than a predetermined voltage difference and the voltage between the output terminal and the second power supply terminal is greater than the predetermined value, the second maximum current level being greater than the first maximum current level.

Current protection method and apparatus and current protected low

A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. A dual-collector lateral junction transistor, formed during the conventional CMOS processing steps used to fabricate the MOS switches, is connected as a voltage clamp between a ground potential and the two bipolar DC output lines of the power supply circuit to assure correct start-up conditions for the circuit. Gain reduction devices are placed in the semiconductor substrate to collect minority carriers which would otherwise be injected into inherent parasitic four layer PNPN junction devices created as a result of the architecture of the circuit, to prevent latch-up of the four layer devices. In a preferred embodiment, an RS-232 receiver and transmitter are contained on the same monolithic integrated circuit as the dual charge pump power supply.

Integrated dual charge pump power supply and RS-232 transmitter/receiver

A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. The unipolar input voltage is placed across a first external transfer capacitor by a first set of MOS switches during a first time period. The unipolar input voltage source is placed in series with the first transfer capacitor and this series combination of voltages is placed across a first external reservoir capacitor by a second set of MOS switches during a second time period. The voltage appearing across the first external reservoir capacitor is placed on a second transfer capacitor during the first time period by a third set of MOS switches. The voltage across the second transfer capacitor is placed into a second external reservoir capacitor with its polarity inverted by a fourth set of MOS switches during the second time period. A dual-collector lateral junction transistor, formed during the conventional CMOS processing steps used to fabricate the MOS switches, is connected as a voltage clamp between a ground potential and the two bipolar DC output lines of the power supply circuit to assure correct start-up conditions for the circuit. Gain reduction devices are placed in the semiconductor substrate to collect minority carriers which would otherwise be injected into inherent parasitic four layer PNPN junction devices created as a result of the architecture of the circuit, to prevent latch-up of the four layer devices. In a preferred embodiment, an RS-232 receiver and transmitter are contained on the same monolithic integrated circuit as the dual charge pump power supply.

The invention relates to an output circuit capable of producing an output signal which may be disabled, leaving the output terminal in a high impedance state capable of being driven externally to a voltage significantly outside the bounds of the output circuit power supply. The output circuit of the invention includes two terminals adapted to be connected to a power supply capable of providing a supply voltage. The output circuit includes an MOS transistor having a substrate, source and drain terminals and a gate, one of the source and drain terminals being coupled to one of the power supply terminals. A second transistor has three terminals including a control terminal and two other terminals, one of which is coupled to the other of the source and drain terminals of the MOS transistor, and the other of which is coupled to the other power supply terminal. An output terminal is coupled between the one terminal of the second transistor and the other of the source and drain terminals of the MOS transistor. A means responsive to an external signal is provided for rendering the output terminal in a high impedance state. A substrate control circuit coupled to the substrate, source and drain terminals of the MOS transistor has a means (1) for detecting whether the voltage at the output terminal is within the voltage range of the power supply, and (2) for controlling the voltage on the substrate of the MOS transistor such that neither its source-substrate nor its drain-substrate junctions can become forward biased, while at the same time providing a voltage capable of disabling both the bipolar and the MOS transistors upon receipt of the external signal. This circuit, unlike prior art circuits, allows the output terminal to be driven significantly beyond the limits of the voltages at the terminals of the power supply, thus permitting its use in 'wired-or' configurations which are important where line driver outputs are used, allowing operation with multiple power supplies having differing voltages, or with no power supply at all.

CMOS amplifier/driver stage with output disable feature

An integrated off-line AC to DC power supply is disclosed. Alternating current (AC) line voltage is supplied (optionally) to an AC voltage to current converter and then (optionally) to a voltage limiter and rectifier which utilizes both MOS devices and inherent junction devices as either a full or half wave rectifier. The rectifier output is supplied to a series-pass junciton device voltage regulator or a regulator which has pre-set voltage output or user-selectable voltage output.

Integrated AC to DC power supply

A bipolar lateral pass-transistor is disclosed for use in MOS integrated circuits. The transistor includes a semiconductor substrate of a first conductivity type covered by an epitaxial layer, a first region of a second conductivity type disposed in the epitaxial layer at a first doping level to a depth of less than the depth of said epitaxial layer, a second region of said conductivity type spaced apart from and surrounding said first region and extending approximately the entire depth of said epitaxial layer having a doping level less than the first doping level and a third region of said second conductivity type spaced apart from and surrounding said second region and extending approximately the entire depth of said epitaxial layer having said first doping level at the surface of said epitaxial layer and said second doping level extending approximately to the bottom of said epitaxial layer. In another aspect of the present invention the bipolar lateral pass-transistor is connected to a voltage source and MOS devices also disposed on the surface of the semiconductor substrate are powered by a voltage which is less than the voltage applied to the lateral pass-transistor, in order to prevent desirable forward biasing of parasitic PN junctions.

Bipolar lateral pass-transistor for CMOS circuits

Integrated dual charge pump power supply and RS-232-transmitter/receiver

Integrated dual charge pump power supply including power down feature

A monolithic integrated circuit containing an inverting/non-inverting voltage doubler charge pump circuit is disclosed for converting a unipolar supply voltage to a bipolar supply voltage of a greater magnitude. The unipolar input voltage is placed across a first external transfer capacitor by a first set of MOS switches during a first time period. The unipolar input voltage source is placed in series with the first transfer capacitor and this series combination of voltages is placed across a first external reservoir capacitor by a second set of MOS switches during a second time period. The voltage appearing across the first external reservoir capacitor is placed on a second transfer capacitor during the first time period by a third set of MOS switches. The voltage across the second transfer capacitor is placed into a second external reservoir capacitor with its polarity inverted by a fourth set of MOS switches during the second time period. A dual-collector lateral junction transistor, formed during the conventional CMOS processing steps used to fabricate the MOS switches, is connected as voltage clamp between a ground potential and the two bipolar DC output lines of the power supply circuit to assure correct start-up conditions for the conduit. Gain reduction devices are placed in the semiconductor substrate to collect minority carriers which would otherwise be injected into inherent parasitic four layer PNPN junction devices created as a result of the architecture of the circuit, to prevent latch-up of the four layer devices. In a preferred embodiment, an RS-232 receiver and transmitter are contained on the same monolithic integrated circuit as the dual charge pump power supply.

A full-wave rectifier circuit is disclosed having two AC input terminals each having connected to it the anode end of a diode equivalent device. The cathode ends of each of the diode equivalent devices are connected together to a positive DC output terminal. Each AC input terminal also has connected to it one end of a switching device. The other ends of each of the switching devices are connected together to a negative DC output terminal. The control means of the switching devices are connected such that only one conducts during any AC half cycle to provide a return path from the negative DC output terminal to the proper one of the two AC input terminals.

Integrated full-wave rectifier circuit

An integrated off-line half-wave rectifier commonly connected to one side of the AC line at one of its output terminals is disclosed. An equivalent diode device passes current to the output during a positive AC input half cycle. A comparator senses the negative half cycle and turns on a switching device to conduct current between the two AC input terminals during that cycle.

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San Jose, CA, United States of America

David Bingham