International Business Machines Corporation

David Bernstein

Michael Rodeh

Martin Edward Hopkins

Jan Civlin

Bilha Mendelson

Itai Nahshon

Gadi Haber

A method for effecting a direct jump in an executable program module to a target address displaced from a source address by a specified distance that is greater than a maximum permitted range. During program linkage the direct jump is split into at least two component direct jumps each no greater than the maximum permitted range, thus allowing the direct jump to be achieved by jumping sequentially from the source address to the target address via each of the component direct jumps. A storage medium for storing data representative of the executable program module contains at least one trampoline for performing the component direct jumps.

Method and storage medium for building very large executable programs

A cache control system and method for operating a computer system which is capable of executing cached and non-cached memory accesses. The cache control system includes a frequency value store for each of a number of memory lines for storing a frequency value indicative of the number of accesses made thereto; an instruction store for storing the index of the last memory line accessed by each of a number of instructions; and control logic which, each time the processor attempts to access a memory location not in the cache memory, tests the frequency value for the last memory line accessed by the current instruction and, if the number of accesses for the memory line exceeds a predetermined threshold, (a) fetches the memory line of the memory location from the main memory into the cache memory and executes a cached memory access, and if not (b) executes a non-cached memory access.

Cache control system and method for selectively performing a non-cache

An instruction scheduler for a computer, capable of speculatively scheduling load instructions by moving certain categories of load instructions in an input instruction sequence from a source block of instructions to a target block of instructions to form an output instruction sequence, the instruction scheduler comprising: logic for selecting a data-independent load instruction as a candidate for rescheduling; logic for determining whether the base register that the load instruction makes use of and/or the contents thereof meets any one of a number of conditions; logic for moving the selected load instruction from the source block to the target block in response to determination that any one of the conditions is met.

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Haifa, Israel

David Bernstein