Texas Instruments Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

David Barry Scott

Uming U Ko

Hugh Thomas Mair

Roderick D Davies

Jiann-Tyng Tzeng

Stefan Rusu

Zhiqiang (Jeff) Wu

Wen-Hao Chen

Wun-Jie Lin

Kuo-Ji Chen

Yu-Ti Su

Hiep V Tran

Po-Chia Lai

Rabiul Islam

Sumanth Katte Gururajarao

Shu-Yi Ying

Abraham Carter

Kuan-Te Li

Yen-Ming Chen

Theodore Warren Houston

Wei Yu Chen

Ta-Pen Guo

Satwinder S Malhi

Chung-Cheng Wu

Min Cao

Roger A Haken

Hsiang-Jen Tseng

Sami Issa

Shyue-Shyh Lin

Alice Wang

Heng-Chih Lin

Shyh-Wei Wang

Steven Swei

Sheng-Jier Yang

Ali Keshavarzi

Sudha Thiruvengadam

Yee-Chaung See

Ka Hing Fung

Stewart M DeSoto

Li-Chun Tien

Baher S Haroun

Chan-Hong Chern

Lee-Chung Lu

Patrick W Bosshart

Ming-Chieh Huang

Amitava Chatterjee

Andrew Marshall

Shivaling S Mahant-Shetti

Xiaowei Deng

Robert H Eklund

Yung-Chin Hou

Shyh-Horng Yang

Christoph A Wasshuber

Shaoping Tang

Gordon Gammie

Franck Benjamin Dahan

Song Zhao

Rolf Lagerquist

Dan M Mosher

Martin J Izzard

Philip C Foreman

Douglas A Prinslow

James D Gallia

George B Jamison

Youngmin Kim

Douglas E Mercer

Tam Minh Tran

Luan A Dang

Jane A Scott

Harold D Goodpaster

Takumi Nasu

Ramesh Venugopal

Radu Avramescu

Ramaprasath Vilangudipitchai

Bing J Sheu

Julianne Heath

Daniel K Meeker

Donald J Coleman, Deceased

Maxwell Mann

Peter H Cumming

An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

Method and system for latch-up prevention

The present invention extends to methods, systems, and computer program products for providing a matching system for correlating accelerometer data to known movements. Data representing known movements can be obtained and stored in a database such as by processing and storing accelerometer data obtained from one or more accelerometers worn by a user while performing a particular movement. The accelerometer data obtained from a particular movement can be processed to generate a feature set descriptive of the accelerations associated with a particular movement or series of movements.

Matching system for correlating accelerometer data to known movements

The present invention is directed to providing customized versions of firmware to a wearable sensor device. The customized versions of the firmware can allow one or more sensors in the wearable sensor device to perform in a manner that is most optimal for a particular user or the particular manner in which the wearable sensor device is used. In some cases, the customizations can include causing the sensors to use a sampling rate that is optimal for one or more activities that the particular user intends to perform while wearing the wearable sensor device.

Updating firmware to customize the performance of a wearable sensor device for a particular use

A method of forming an integrated circuit including forming a first diffusion area and a second diffusion area on a substrate, wherein the first diffusion area is configured for a first type transistor, the second diffusion area is configured for a second type transistor. The method further includes forming first source and drain regions in the first diffusion area. The method further includes forming second source and drain regions in the second diffusion area. The method further includes forming a gate electrode extending across the first diffusion area and the second diffusion area. The method further includes forming a first metallic layer, a second metallic layer, and a third metallic layer. The first metallic layer is electrically coupled with the first source region. The second metallic layer is electrically coupled with the first and second drain regions. The third metallic layer is electrically coupled with the second source region.

Integrated circuits and manufacturing methods thereof

The present invention extends to methods, systems, and computer program products for providing diet and exercise plans and for providing real time tracking and notifications of the user's conformance with a plan. The plan can be dynamically updated in real time based on the user's compliance with the plan. In some embodiments, the present invention can be implemented using a user's mobile phone that communicates with one or more other computing devices that are incorporated into exercise devices.

Providing diet and exercise plans with real time tracking, modification, and notification

A memory circuit including at least one memory array and at least one sleep transistor connected to the at least one memory array and connected to a first power line for providing a first power voltage. The memory circuit further includes at least one diode-connected transistor directly connected to the at least one memory array and directly connected to the first power line and a back-bias circuit electrically coupled with a bulk of the at least one diode-connected transistor.

Memory circuits having a diode-connected transistor with back-biased control

An integrated circuit layout includes a standard cell, which includes a first gate strip and a second gate strip parallel to each other and having a gate pitch; a first boundary and a second boundary on opposite ends of the first standard cell; and a third boundary and a fourth boundary on opposite ends of the first standard cell and parallel to the first gate strip and the second gate strip. A cell pitch between the third boundary and the fourth boundary is not equal to integer times the gate pitch. A PMOS transistor is formed of the first gate strip and a first active region. An NMOS transistor is formed of the first gate strip and a second active region.

Standard cells having flexible layout architecture/boundaries

An energy harvesting system includes a plurality of transducers. The transducers are configured to generate direct current (DC) voltages from a plurality of ambient energy sources. A sensor control circuit has a plurality of sensors configured to detect the DC signals from the plurality of transducers. A DC-to-DC converter is configured to supply an output voltage. A plurality of switches, each switch coupled between the DC-to-DC converter and a corresponding transducer of the plurality of transducers. The sensor control circuit enables one switch of the plurality of switches and disables the other switches of the plurality of switches based on a priority criterion.

Method and apparatus for energy harvest from ambient sources

A memory circuit includes at least one memory array. At least one sleep transistor is electrically coupled between the at least one memory array and a first power line for providing a first power voltage. At least one diode-connected transistor is electrically coupled between the at least one memory array and the first power line. A back-bias circuit is electrically coupled with a bulk of the at least one diode-connected transistor.

An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is spaced from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. The first metallic layer is electrically coupled with the first source region. The first metallic layer and the first diffusion area overlap with a first distance. A second metallic layer is electrically coupled with the first drain region and the second drain region. The second metallic layer and the first diffusion area overlap with a second distance. The first distance is larger than the second distance.

A method for generating model files of target devices of an integrated circuit includes providing the target devices; providing a device target set for the target devices, wherein the device target set comprises target values of parameters of the target devices; determining a nearest known model related to the target devices, wherein the nearest known model comprises a first model file; performing a sensitivity analysis to determine sensitive parameters in the first model file; modifying the sensitive parameters in the first model file to generate a second model file; and determining a fitness value of a circuit simulated using the second model file with values of parameters in the device target set.

Generating models for integrated circuits with sensitivity-based minimum change to existing models

A head-positioning aid for treating or preventing plagiocephaly and torticollis is formed of a soft, compliant beanie-style cap. A soft and pliable deflector is attached to the beanie cap and extends downward from near the apex to near the lower edge of the cap. The cap is applied on an infant's head in an orientation to place the deflector at any required position about the circumference of the head. The cap and deflector are united by themed indicia designed to bring family acceptance of the cap to promote acceptance and thereby support long term usage, as may be required.

Head positioning aid

In a method and system for data retention, a data input is latched by a first latch. A second latch coupled to the first latch receives the data input for retention while the first latch is inoperative in a standby power mode. The first latch receives power from a first power line that is switched off during the standby power mode. The second latch receives power from a second power line. A controller receives a clock input and a retention signal and provides a clock output to the first latch and the second latch. A change in the retention signal is indicative of a transition to the standby power mode. The controller continues to hold the clock output at a predefined voltage level and the second latch continues to receive power from the second power line in the standby power mode, thereby retaining the data input.

Ultra low area overhead retention flip-flop for power-down applications

Growing community of inventors

Plano, TX, United States of America

David Barry Scott