Stmicroelectronics (crolles 2) Sas

David Barge

Pierre Morin

Yves Campidelli

Philippe Garnier

Olivier Gourhant

Clément Gaumer

Mickaël Gros-Jean

An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOI substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.

Method for fabricating NMOS and PMOS transistors on a substrate of the SOI, in particular FDSOI, type and corresponding integrated circuit

An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer.

Insulation wall between transistors on SOI

A method for forming the gate insulator of a MOS transistor, including the steps of: a) forming a thin silicon oxide layer at the surface of a semiconductor substrate; b) incorporating nitrogen atoms into the silicon oxide layer by plasma nitridation at a temperature lower than 200&#xb0; C., to transform this layer into a silicon oxynitride layer; and c) coating the silicon oxynitride layer with a layer of a material of high dielectric constant, wherein steps b) and c) follow each other with no intermediate anneal step.

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Grenoble, France

David Barge