Advanced Micro Devices Corporation

David Balmforth

Ching Yu

Din-I Tsai

Pierre F Haubursin

A system for tracing read and write accesses to selected registers is provided in a network interface. The system has a read trace register containing a separate bit for each register to be monitored for read access by an external CPU. A write trace register is provided with a bit for each register to be monitored for write access by the CPU. When the CPU performs read or write access to a monitored register, a decoder that decodes an address signal from the CPU produces a trace select signal supplied to the read trace register and/or write trace register. In response to the trace select signal, the bit representing the monitored register is set to a predetermined logic state indicating that the monitored register was accessed by the CPU for reading and/or writing.

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Mountain View, CA, United States of America

David Balmforth