Intel Corporation

Hewlett-packard Development Company, L.p.

David Bach

Simon C Steely, Jr

Richard J Dischler

Benjamin Keen

William J Butera

Christian Karl

Olivier Franza

Brian Leung

Kaladhar Radhakrishnan

Cengiz Ahmet Palanduz

Timothe Litt

Sharad M Shah

Christopher C Jones

Larry Binder

Angelo Villani

Nicholas Palmer

Simon C Steely Jr

Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.

Layered super-reticle computing : architectures and methods

Layered super-reticle computing: architectures and methods

A ceramic package substrate has a recess. This allows a device in that recess to be close to a die attached to the substrate's top side, for better performance. The device may be an array capacitor, an in-silicon voltage regulator, or another device or devices.

Ceramic package substrate with recessed device

A method and apparatus that allows additional contact pads to be added to a package to support debug and test operations is disclosed. In a preferred embodiment, a circuit board apparatus includes a semiconductor package and an interposer for receiving the semiconductor package. The semiconductor package preferably includes a substrate having a matrix of conductive contact pads on both the top and bottom surfaces of the substrate. The interposer preferably includes a body having a matrix of interposer contact bumps on both the inner and outer surfaces of the body. Each interposer contact bump preferably includes a metal coating and is shaped to abut a contact pad of the semiconductor package.

Dual interposer packaging for high density interconnect

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Shrewsbury, MA, United States of America

David Bach