Advanced Micro Devices Corporation

Other

Analog Devices,inc.

Intel Corporation

David B Witt

Thang M Tran

William M Johnson

Michael D Goddard

Marty Lynn Pflum

Rajiv M Hattangadi

James B Keller

Derrick R Meyer

Brian D McMinn

Ravi Kolagotla

Murali S Chinnakonda

Brett B Stewart

Michael J Allen

Rupaka Mahalingaiah

James K Pickett

Lawrence A Booth

Bradley C Aldrich

William C Anderson

Gopi Ganapathy

Hebbalalu S Ramagopal

Moinul Syed

Thomas P Scott

Bo A Molander

Michael Allen

A register file architecture in a general purpose digital signal processor (DSP) supports alignment independent SIMD (Single Instruction/Multiple Data) operations. The register file architecture includes a register pair and an alignment multiplexer. Two 32 bit grouped words may be loaded into the register pair. Each grouped word includes four 8 bit operands. The alignment state of the 32 bit words may be determined by the two least significant bits (LSBs) of the pointer addresses of the grouped words. These LSBs are used to control the alignment MUX to select n operands from the two 32 bit grouped words and output an aligned 32 bit grouped word to execution units for parallel processing.

General purpose register file architecture for aligned simd

A digital data processor having a main pipeline to which a side pipe is loosely coupled. In particular, the side pipe is coupled to the main pipeline at a point after which an instruction entering the side pipe cannot cause an exception. When such an instruction enters the first stage of the side pipe, a copy or 'ghost' of this instruction is created. While the actual instruction flows down the side pipe, this ghost instruction is allowed to flow independently down the main pipeline as if it were a non-squashable no-op. When the ghost reaches the retirement stage of the main pipeline, it is retired in normal program order, regardless of the status of the actual instruction. However, in addition, each system resource that is still waiting for a result from the actual instruction is marked appropriately. When the actual instruction finally completes in the side pipe, the only consequence, other than those local to the side pipe itself, is that any results are forwarded to the awaiting resources. If it should happen that a resource has been reallocated to a more recent instruction while the actual instruction is still in flight, the forwarded result is discarded upon arrival; otherwise, the resource is updated using the forwarded result. As a result of employing such a pipe coupling mechanism, the number of pipe stages that must be traversed by instructions other than those requiring a side pipe resource may be reduced. One disclosed example of such a side pipe is a multiply accumulate unit suitable for use in digital signal processing applications, whereby the performance of control type instructions is greatly improved.

Pipelined processor including a loosely coupled side pipe

A two-stage, pipelined modulo address generator (MAG) ( &prime;) for generating from a current pointer into a circular buffer of size L, a next pointer into the buffer, is comprised of a pointer generation stage ( &prime;) and a modulo correction and pointer selection stage ( &prime;), each adapted to operate in a selected one of two modes. In the first operating mode: the pointer generation stage ( &prime;) generates a sequential pointer which is a selected offset from the current pointer; and the modulo correction and pointer selection stage ( &prime;) generates, modulo L, a modulo corrected sequential pointer, and provides as the next pointer the sequential pointer, if it is in the buffer, and the modulo corrected sequential pointer, otherwise. In the second operating mode: the pointer generation stage ( &prime;) generates a lookahead pointer which is twice the selected offset from the current pointer; and the modulo correction and pointer selection stage ( &prime;) generates, modulo L, a modulo corrected lookahead pointer and, modulo 2L, a double-modulo corrected lookahead pointer, and provides as the next pointer the lookahead pointer, if it is in the buffer, the modulo corrected lookahead pointer, if the lookahead pointer is not in the buffer but the modulo corrected lookahead is in the buffer, and the double-modulo corrected lookahead pointer, otherwise.

Modulo address generation method and apparatus

A processor employs an instruction queue and a dependency vector generation unit. The dependency vector generation unit generates a dependency vector for each instruction operation. Particularly, a dependency vector corresponding to a first instruction operation may be indicative of an ordering dependency between the first instruction operation and a prior instruction operation even if the first instruction operation does not have an operand dependency on the prior instruction operation. The instruction queue inhibits dependencies until each dependency within the dependency vector is satisfied.

Universal dependency vector/queue entry

A processor includes a first instruction cache, a second instruction cache, a return stack, and a fetch unit. The return stack is configured to store return addresses corresponding to call instructions. The return stack is configured to output a first return address from a top of the return stack and a second return address which is next to the top of the return stack. The fetch unit is coupled to the first instruction cache, the second instruction cache, and the return stack, and is configured to convey the first return address to the first instruction cache responsive to a return instruction. Additionally, the fetch unit is configured to convey the second return address to the second instruction cache responsive to the return instruction.

Processor including efficient fetch mechanism for L0 and L1 caches

The present invention is an apparatus for monocular head displays, which enables a compact, light in weight, sturdy apparatus that has a wide angle of viewing, a bright and sharp image display that operates on low voltage in a wide range of temperatures. The image is bright and high in contrast. Due to the compactiveness and wide viewing angle, it is readily useable inside helmets and goggles and visors. The signals that can be used include data, maps, graphics or video images including infrared or other images. Because of the wide viewing angle, the module may be placed and adjusted for multiple users and field installation.

Detachable monocular display

The processor is configured to predecode instruction bytes prior to their storage within an instruction cache. During the predecoding, relative branch instructions are detected. The displacement included within the relative branch instruction is added to the address corresponding to the relative branch instruction, thereby generating the target address. The processor replaces the displacement field of the relative branch instruction with an encoding of the target address, and stores the modified relative branch instruction in the instruction cache. The branch prediction mechanism may select the target address from the displacement field of the relative branch instruction instead of performing an addition to generate the target address. In one embodiment, relative branch instructions having eight bit and 32-bit displacement fields are included in the instruction set executed by the processor. Additionally, the processor employs predecode information (stored in the instruction cache with the corresponding instruction bytes) including a start bit and a control transfer bit corresponding to each instruction byte. The combination of the start bit indicating that the byte is the start of an instruction and the corresponding control transfer bit identifies the instruction as either a branch instruction or a non-branch instruction. For relative branch instructions including an eight bit displacement, the control transfer bit corresponding to the displacement field is used in conjunction with the displacement field to store the encoded target address. Thirty-two bit displacement fields store the entirety of the target address, and hence the encoded target address comprises the target address.

Processor configured to predecode relative control transfer instructions and replace displacements therein with a target address

An apparatus having a core processor and a memory system is disclosed. The core processor includes at least one data port. The memory system is connected in such a way as to provide substantially simultaneous data accesses through the data port. The memory system can be made user configurable to provide appropriate memory model.

System having a configurable cache/SRAM memory

An instruction alignment unit is provided which is capable of routing variable byte length instructions simultaneously to a plurality of decode units which form fixed issue positions within a superscalar microprocessor. The instruction alignment unit may be implemented with a relatively small number of cascaded levels of logic gates, thus accomodating very high frequencies of operation. In one embodiment, the superscalar microprocessor includes an instruction cache for storing a plurality of variable byte-length instructions and a predecode unit for generating predecode tags which identify the location of the start byte of each variable byte-length instruction. An instruction alignment unit is configured to channel a plurality of the variable byte-length instructions simultaneously to predetermined issue positions depending upon the locations of their corresponding start bytes in a cache line. The issue position or positions to which an instruction may be dispatched is limited depending upon the position of the instruction's start byte within a line. By limiting the number of issue positions to which a given instruction within a line may be dispatched, the number of cascaded levels of logic required to implement the instruction alignment unit may be advantageously reduced.

Instruction alignment unit for routing variable byte-length instructions

A register renaming apparatus includes one or more physical registers which may be assigned to store a floating point value, a multimedia value, an integer value and corresponding condition codes, or condition codes only. The classification of the instruction (e.g. floating point, multimedia, integer, flags-only) defines which lookahead register state is updated (e.g. floating point, integer, flags, etc.), but the physical register can be selected from the one or more physical registers for any of the instruction types. Determining if enough physical registers are free for assignment to the instructions being selected for dispatch includes considering the number of instructions selected for dispatch and the number of free physical registers, but excludes the data type of the instruction. When a code sequence includes predominately instructions of a particular data type, many of the physical registers may be assigned to that data type (efficiently using the physical register resource). By contrast, if different sets of physical registers are provided for different data types, only the physical registers used for the particular data type may be used for the aforementioned code sequence. Additional efficiencies may be realized in embodiments in which an integer register and condition codes are both updated by many instructions. One physical register may concurrently represent the architected state of both the flags register and the integer register. Accordingly, a given functional unit may forward a single physical register number for both results.

Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values

A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated whenever one or more instructions are dispatched. A microprocessor employing the reorder buffer is also configured with fixed, symmetrical issue positions. The symmetrical nature of the issue positions may increase the average number of instructions to be concurrently dispatched and executed by the microprocessor. The average number of unused locations within the line decreases as the average number of concurrently dispatched instructions increases. One particular implementation of the reorder buffer includes a future file. The future file comprises a storage location corresponding to each register within the microprocessor. The reorder buffer tag (or instruction result, if the instruction has executed) of the last instruction in program order to update the register is stored in the future file. The reorder buffer provides the value (either reorder buffer tag or instruction result) stored in the storage location corresponding to a register when the register is used as a source operand for another instruction. Another advantage of the future file for microprocessors which allow access and update to portions of registers is that narrow-to-wide dependencies are resolved upon completion of the instruction which updates the narrower register.

Line-oriented reorder buffer configured to selectively store a memory operation result in one of the plurality of reorder buffer storage locations corresponding to the executed instruction

A processor employs a first instruction cache, a second instruction cache, and a fetch unit coupled to the first instruction cache and the second instruction cache. The fetch unit generates a branch target address responsive to a branch instruction which includes a displacement. Additionally, the fetch unit selects one of the first instruction cache and the second instruction cache from which to fetch instructions stored at the branch target address responsive to a size of the displacement.

Disclosed is a circuit and method for multiple access of a branch history table during a single clock cycle. In accordance thereto, a first branch history table index is generated which is used for accessing the branch history table. A first counter value is read from the branch history table in response to accessing the branch history table using the first branch history table index. A second branch history table index is also generated for accessing the branch history table. A pair of counter values are read from the branch history table in response to accessing the branch history table using the second branch history table index. One of the pair of counter values is selected based upon the value of the first counter value read from the branch history table. The first and second counter values in turn are used for predicting corresponding first and second branch instructions. The first and second branch history table indexes are generated in the same cycle. Likewise, the first counter value and the pair of counter values are read from the branch history table in the same clock cycle. Lastly, the second counter value is selected from the pair of counter values in the same cycle.

Method and circuit for single cycle multiple branch history table access

A processor is configured to generate lookahead values using a cumulative constant. The processor classifies operations to a particular register (e.g. the stack pointer register, or ESP in an embodiment employing the x86 instruction set architecture) as either accelerated or non-accelerated. For example, instructions which are defined to increment/decrement the particular register by an explicit or implicit constant value may be accelerated operations. Upon the occurrence of a non-accelerated operation, the processor may begin accumulating the cumulative effect of accelerated operations to the result of the non-accelerated operation as a cumulative offset. The result of the non-accelerated operation (upon execution thereof) may then be added to the cumulative offset values corresponding to each accelerated operation to generate the particular register value corresponding to that accelerated operation. Accordingly, dependencies upon the register due to the accelerated operations may be alleviated. Accelerated operations may execute in parallel upon provision of the value generated by the non-accelerated operations.

Cumulative lookahead to eliminate chained dependencies

A line predictor is configured to speculatively fetch instructions following a branch instruction. The line predictor stores a plurality of lines that each contain instruction line information. Each line stored by the line predictor includes a fetch address, information regarding one or more instructions, and one or more next fetch addresses. In response to receiving a fetch address, the line predictor is configured to provide instruction line information corresponding to the one or more instructions located at the fetch address to an alignment unit. The line predictor is also configured to provide a next fetch address associated with the fetch address to an instruction cache for speculative fetching and to a branch prediction unit for a branch prediction. The next fetch address is further fed back into the line predictor to generate the instruction line information associated with it and a subsequent next fetch address. A next fetch address may be the sequential address following the last instruction associated with the instruction line information of the fetch address. If an instruction within the instruction line information of the fetch address is a branch instruction, however, the next fetch address may be the target address of the branch instruction. The branch prediction unit is configured to generate a branch prediction in response to receiving a next fetch address if a branch instruction is detected in the instruction line information of the next fetch address. The branch prediction is then compared to a subsequent next fetch address. If the branch prediction differs from a subsequent next fetch address, operations that were initiated using the subsequent next fetch address are canceled, the subsequent next fetch address is updated in the line predictor, and the updated subsequent next fetch address is refetched.

Growing community of inventors

Austin, TX, United States of America

David B Witt