Xilinx, Inc.

David B Squires

Ralph D Wittig

Jennifer Wong

Goran Hk Bilski

David P Schultz

Brian Taylor Brunn

F Erich Goetting

James M Simkins

Brian Karl Seemann

Goran Bilski

Normand T Lemay, Jr

Thomas Anthony Lee

Daniel J Ferris, Iii

A computer-readable medium is encoded with a computer program for directing a computer to convert a first bitstream operable to configure, for example, an earlier-generation PLD to a second bitstream operable to configure, for example, a later-generation PLD, wherein functionality is preserved from one PLD to another. The computer divides each PLD into similar regions, and replicates a function of each region of the first PLD in a corresponding region of the second PLD. The computer interconnects the regions of the second PLD to replicate the interconnections of the regions of the first PLD. The computer allows a user to manipulate the connection scheme of the second PLD.

Backward compatible PLDs

A data conveyance integrated system that can be utilized in a base station and/or end user devices in a wireless communication system. The integrated system includes first and second integrated circuits (ICs). The first IC includes a first serial-deserial (SERDES) module, a transmit radio frequency module, and a receive radio frequency module. The transmit and receive radio frequency modules provide the wireless communication between the base stations and end user devices. The second IC includes a second SERDES module and a programmable logic fabric programmed to implement one or more wireless communication functions. Accordingly, the programmable logic fabric generates outbound digital signals from data (e.g., video, audio, control, or text data) provided to the device, and/or processes inbound digital signals to recapture the originally transmitted data. Thus, base stations and/or end user devices within a wireless communication system can be readily reconfigured.

Radio frequency data conveyance system including configurable integrated circuits

Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create specialized logic blocks including a RAM, a processor, and a dedicated interface coupled between the RAM, the processor, and the general interconnect structure of the PLD. The additional area is obtained by increasing the width of the column of BRAM blocks. Because the interconnect structure remains virtually unchanged, the interconnections between the specialized logic blocks and the adjacent tiles are already in place, and the modifications do not affect the PLD routing software. In some embodiments, the processor can be optionally disabled, becoming transparent to the user. Other embodiments provide methods of modifying a PLD to include the structures and provide the capabilities described above.

Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks

A single integrated circuit can be designed to include a processor core and one or more configurable peripheral devices selectable by a user. Because the peripheral device is configurable, the user can select only the features he/she needs in the integrated circuit. As a result, the peripheral devices included in the integrated circuit do not have to be flexibly designed in the same manner as commercially available peripheral devices. Consequently, they are easy to use.

Configurable peripheral devices

A method for providing a core for a programmable logic device (PLD) is provided. In this method, a vendor can designate the size and ports of a core. Using this information, a user can generate a top-level design that can accommodate the core. The user can then submit that top-level design to the vendor, or a third party designated by the vendor, to generate a complete configuration bitstream for the PLD. The user can use this configuration bitstream to program the PLD, thereby implementing the top-level design including the core. The number of bits in this configuration bitstream is typically large enough to render reverse engineering economically unfeasible. Thus, the method allows vendors to retain control over their proprietary core IP and discourages undetectable use of this IP.

Method for providing pre-designed modules for programmable logic devices

A method and apparatus for creating and utilizing a database of defective antifuses on a programmable logic device and comparing the list to a catalog of required connections in a design, wherein the process of comparing the two lists will determine whether the device, although flawed, is nonetheless compatible with the design to be implemented, thereby increasing device yield.

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Palo Alto, CA, United States of America

David B Squires