Ncr Corporation

David B Schuck

James E Kocol

Robert O Gunderson

Daniel J Marro

Kasun K Chan

James W Stone

Gerald J Erickson

James C Kocol

A data processing system employing broadcast packet switching and having a plurality of subsystems and a system bus for linking the subsystems. The subsystems are grouped within stations that are each enclosed by a computer cabinet. The system bus includes a star coupler, first and second external transmission lines connecting each station to the star coupler, and first and second internal transmission lines within each station that are coupled to the first and second external transmission lines. The subsystems within each station are each coupled to the first and second internal transmission lines by a system bus interface. The system bus interface monitors the system bus for an idle condition, and passes a message from its subsystem to the system bus only when it detects an idle condition on the system bus. Each message on the system bus includes a postamble that is garbled by any system bus interface that detects an error in any message on the system bus. Each subsystem has a local memory that includes a mailbox for storing header information of messages that are to be copied by that subsystem. DMA circuitry in each system bus interface manages the operation of the mailbox in its subsystem. In alternate embodiments, the star coupler may be a magnetic star coupler or an electrical star coupler, and the system bus may be comprised of two channels, each channel including a star coupler and pairs of transmission lines connecting each station to the star coupler.

Data processing system wherein all subsystems check for message errors

Data processing system employing broadcast packet switching

A method and apparatus for simulating custom chips to be used in a data processing system. Each chip is simulated by a chip simulator that includes a mother board and a plurality of baby boards mounted and interconnected on the mother board. Each baby board has circuit components mounted thereon for performing the circuit function of one cell of the chip. Chip simulators are interconnected in an interconnecting apparatus that supports the mother boards in parallel and spaced apart relation. Chip simulators that represent all of the chips found on a single printed circuit board in the system are interconnected at the interconnecting apparatus so that design errors which are only evident when the chips are interconnected can be tested for and detected prior to fabrication of the chips.

Method for simulating and testing an integrated circuit chip

Data processing system having dual-channel system bus

A connector for connecting coplanar circuit boards in an edge-to-edge fashion. The connector has a housing with a circuit board receiving cavity extending through and between opposite faces of the housing. The cavity has two opposing side walls which support electrical terminals for contacting conductors on the edges of circuit boards that are inserted into the cavity at the opposing faces of the housing. A passage extends transversely through the housing and intersects the cavity and receives a pin for engaging the terminals and maintaining them fixed within the housing. The edge-to-edge connection of two or more coplanar circuit boards is provided by use of the connector.

Connector for interconnecting circuit boards

The present invention relates to an integrated circuit package for flat circuit elements such as an integrated circuit chip and an electrical connector for receiving such integrated circuit package. The integrated circuit package comprises a round ceramic carrier or substrate upon which an integrated circuit chip is mounted. The electrical connector of the present invention is a cylindrically shaped hollow socket, the inside diameter of the socket being large enough such that the ceramic substrate may be placed in the hollow. The inside cylindrical wall contains resilient pin-like connections arranged in a circle therein for making contact with a corresponding conductor of the integrated circuit package. The outside surface of the cylindrically shaped electrical connector is threaded for receiving a cap which holds the integrated circuit package against the resilient pin-like connections.

VLSI Packaging system

Data processing system wherein at least one subsystem has a local memory

A data processing system that has a plurality of subsystems connected to a system bus includes diagnostic circuitry for isolating a fault at one of the subsystems. The diagnostic circuitry includes a multiplexer at the output gates of each subsystem to the system bus and diagnostic selection circuitry at a bus controller that provides a select signal to each multiplexer. When selected, the multiplexer is connected to pass a 'high' logic level signal to an associated bit line of the system bus. When a bit line of the system bus is 'stuck high,' because of a fault at the output of one of the subsystems, the diagnostic circuitry selectively connects each subsystem to the bit line of the system bus in order to provide a 'high' logic level signal to that bit line. A test interface and A/D converter are connected to the bit line, and if a voltage level change is detected after a subsystem is connected, the connected subsystem is not the one having the fault. If no voltage level change is detected, it is known that that subsystem is the faulty one.

Diagnostic circuitry for isolating a faulty subsystem in a data

A self-correcting memory system includes internal error detection and correction circuitry that periodically accesses each data word and a group of ECC check bits associated with each data word stored in the memory system. The error detection and correction circuitry includes an ECC checking circuit that receives the accessed data word, generates ECC bits, and compares those ECC bits to the group of ECC check bits associated with the data word. The resulting signal is used to correct any single bit in error, and to indicate the presence of a double bit error. A self-correct address counter is cascaded to a refresh address counter in the control circuitry of the memory system so that the accessing of each data word occurs during a refresh cycle of the memory system.

Self-correcting memory system

A pipelined computer which executes high level language instructions is disclosed. The pipelined computer includes a memory for storing the high level language instructions therein. A plurality of microprogrammed digital computers are coupled in parallel to the memory, and are also intercoupled via an interlocking bus. The microprogrammed computers, in conjunction with the interlocking bus, form a pipeline for executing the high level language instructions. Each of the computers is a separately microprogrammable stage of the pipeline.

Pipelined computer

An optical by-pass relay for use with an optical transmission line wherein transmitted optical energy is focused on a light detector for conversion into an electrical signal which electrical signal is coupled to a utilization device. A light emitter coupled to the utilization device, transmits lights onto the transmission line to thereby place the utilization device into the optical transmission line. Means are provided for displacing the detector and emitter from the optical path of the transmission line and for positioning an optical coupler such as a glass rod into the optical path to thereby by-pass the utilization device while providing continuity to the optical signal traversing the optical transmission line.

Growing community of inventors

Escondido, CA, United States of America

David B Schuck