Hughes Aircraft Company

Hughes Electronics Corporation

University of California

David B Rensch

Mehran Matloubian

Lawrence E Larson

William E Stanchina

Jack Y Josefowicz

Perry A Macdonald

Debabani Choudhury

Kai-Wei Nieh

James A Foschaar

Phillip H Lawyer

Robert A Metzger

Cheng P Wen

Angelos Alexanian

Robert Armstrong York

Meir Bartur

Michael G Case

Vladimir Rodov

Chan-Shin Wu

Madjid Hafizi

Jeffrey B Shealy

John Y Chen

Debra Marr-Leisy

Cheng-Keng Pao

Mary Y Chen

A low cost highly integrated method of fabricating a heat sink on the backside of a power semiconductor device maintains device performance, improves thermal transfer, and enables reliable planar connections without having to dice the wafer or package the discrete device-heat sink assembly. An etch stop layer is formed between the wafer and the frontside power devices to protect them during backside processing and to reduce the contact resistance between the device and its heat sink. The heat sinks are formed by thinning, patterning and then plating the wafer in such a manner that the devices can be released without dicing. The heat sinks are preferably oversized so that a vacuum tool can grasp the heat sink from above without damaging the device and then compression bond the heat sink onto a planar microstrip circuit assembly, which is designed and packaged to facilitate easy replacement of failed devices.

Fabrication of high power semiconductor device with a heat sink and integration with planar microstrip circuitry

Fabrication of high power semiconductor devices with respective heat

A combined test fixture and spatial-power-combined amplifier includes a base, a first waveguide mounting flange engaged to said base, a second waveguide mounting flange engaged to said base, a waveguide input fixed to said first flange, a waveguide output fixed to said second flange, an amplifier array disposed between said first flange and second flange, said array comprising a plurality of semiconductors for amplifying a signal, and a spacer for spacing apart said semiconductors. A plurality of amplifier cards constitute the array, with the cards being disposed in various arrangements which include a linearly stacked arrangement and radially stacked arrangement. The first and second waveguide mounting flanges are constructed to slide along the base to enable the amplifier array to be easily changed.

Universal fixture/package for spatial-power-combined amplifier

A microwave/millimeter wave circuit structure supports discrete circuit elements by flip-chip mounting to an interconnection network on a low cost non-ceramic and non-semiconductor dielectric substrate, preferably Duroid. The necessary precise alignment of the circuit elements with contact pads on the substrate network required for the high operating frequencies is facilitated by oxidizing the interconnection network, but providing the contact pads from a non-oxidizable material to establish a preferential solder bump wetting for the pads. Alternately, the contact bumps on the flip-chips can be precisely positioned through corresponding openings in a passivation layer over the interconnection network. For thin circuit substrates that are too soft for successful flip-chip mounting, stiffening substrates are laminated to the circuit substrates. In a self-contained antenna application in which two of the circuit substrates are laminated together, with an antenna on one side and circuitry on the other side, a metallic ground plane between the substrates also serves a stiffening function.

Microwave/millimeter wave circuit structure with discrete flip-chip

A multi-layer collector heterojunction transistor (10) provides for high power, high efficiency transistor amplifier operation, especially in the RF (radio frequency) range of operation. A larger band gap first collector layer (12), approximately 15% of the active collector region (11) thickness, is provided at the base-collector junction (13). A smaller band gap second collector layer (14) forms the remainder of the active collector region (11). The multi-layer collector structure provides higher reverse bias breakdown voltage and higher carrier mobility during relevant portions of the output signal swing. A lower saturation voltage limit, or 'knee' voltage, is provided at the operating points where linear operating regions transition to saturation operating regions as depicted in the output voltage-current (I-V) characteristic curves. The magnitude of the output signal swing of an amplifier may be increased, providing higher power amplification with greater power efficiency. The power supply voltage for the amplifier may be increased, providing for the use of a smaller, lighter power supply.

Multi-layer collector heterojunction transistor

A high speed diode with a low forward-bias turn-on voltage is formed by a heterojunction between a layer of doped semiconductor material that has a narrow bandgap energy of not more than about 0.4 eV, and a layer of oppositely doped semiconductor material that has a substantially wider bandgap energy. The device operates with a lower turn-on voltage than has previously been attainable, despite lattice mismatches between the two materials that can produce strain and substantial lattice dislocations in the low bandgap material. The two materials are selected so that the valence and conduction band edge discontinuities at the heterojunction enable a forward carrier flow but block a reverse carrier flow across the junction under forward-bias conditions. Preferred material systems are InAs for the narrow bandgap material, InGaAs for the wider bandgap material and InP for the substrate, or AlSb for the wider bandgap material and GaSb for the substrate. A compositional grading can be provided at the heterojunction to reduce energy band spikes, and a region of low dopant concentration is included in the wider bandgap material to increase the diode's reverse-bias breakdown voltage.

Heterojunction diode with low turn-on voltage

A monolithic microwave integrated circuit is formed by positioning a distributed, transmission-line network over a microwave-device structure. The ground plane of the transmission-line network adjoins an interconnect system of the microwave-device structure and signal lines of the transmission-line network are adapted to communicate with the microwave-device structure through orifices of the ground plane. The invention facilitates the use of low-cost silicon-based transistors in monolithic microwave integrated circuits.

Monolithic microwave integrated circuit and method

An electrical junction is precisely located between a highly p doped semiconductor material and a more lightly n doped semiconductor material by providing a lightly p doped buffer region between the two materials, with a doping level on the order of the n doped material's. The buffer region is made wide enough to establish an electrical junction at approximately its interface with the n doped material, despite a diffusion of dopant from the p doped material. When applied to a heterojunction bipolar transistor (HBT), the transistor's base serves as the heavily p doped material and its emitter as the more lightly n doped material. The buffer region is preferably employed in conjunction with a graded superlattice, located between the buffer and emitter, which inhibits dopant diffusion from the base into the emitter. A p-n junction is formed within the superlattice, which functions on one side as an electrical extension of the emitter and on the other side as an electrical extension of the buffer, and establishes the electrical junction at the p-n junction location. The precise positioning of the electrical junction results in a known and repeatable emitter-base turn-on voltage.

Electrical junction device with lightly doped buffer region to precisely

An oxide superconductor having a high critical temperature is provided with a passivation coating comprising a first layer of a Group II oxide, such as magnesium oxide, and a second layer of a polymer, such as polyimide. The Group II oxide is formed under conditions to be substantially amorphous. After depositing the Group II, layer, the encapsulated superconductor is heated to an elevated temperature for a period of time in an oxidizing atmosphere. This restores the high critical temperature to its original value. The polymer is then coated on top of the Group II oxide and cured. The passivation coating is resistant to strong acids, strong bases, and water, is robust, hard, and resilient against scratching.

Passivation of thin film oxide superconductors

An oxide superconductor having a high critical temperature is provided with a passivation coating comprising a first layer of a Group II oxide, such as magnesium oxide, and a second layer of a polymer, such as polyimide. The Group II oxide is formed under conditions to be substantially amorphous. After depositing the Group II layer, the encapsulated superconductor is heated to an elevated temperature for a period of time in an oxidizing atmosphere. This restores the high critical temperature to its original value. The polymer is then coated on top of the Group II oxide and cured. The passivation coating is resistant to strong acids, strong bases, and water, is robust, hard, and resilient against scratching.

A GaAs circuit structure is described which interposes a Langmuir-Blodgett (L-B) layer between the substrate and a conductive contact. The thickness of the layer is controlled to determine the operating characteristics of the device. The head group of the L-B molecule is chosen so that it passivates the surface states of the particular GaAs substrate being used. Certain preferred acids and amino head groups are disclosed. The L-B layer has been found to both increase the gate barrier height for an FET, and to passivate dangling bonds and surfaces defects in the GaAs substrate to enable inversion mode operation. Specific FET and diode devices are described.

Process of making GaAs electrical circuit devices with Langmuir-Blodgett

A thin conducting line such as a gate pattern is defined on a semiconductor chip (10) by applying a narrow ion beam, suitably a focused-ion-beam (16) having a submicrometer thickness from a source (18) onto a thin layer (14) of an inorganic material such as silicon or aluminum overlying a layer (12) of refractory metal on a substrate (11). The ion beam is translated to form a gate pattern at a dose between about 0.1 to 50.times.10.sup.15 cm.sup.-2 and an energy from about 1 to 1000 KeV. Ions are implanted into the silicon and aluminum layers and into the underlying portions of the refractory metal layer and to render the exposed portions of the layers preferentially resistant to wet-etchant. The portions of layers which are not exposed nor protected by layers which are exposed, are preferentially removed to form a gate. Conventional MOSFET or MESFET processing to implant ions to form source and drain regions may then be performed.

Growing community of inventors

Thousand Oaks, CA, United States of America

David B Rensch