California Institute of Technology

Hewlett-packard Company

Other

David B Kirk

Alan H Barr

Olin G Lathrop

Douglas A Voorhies

Brooke P Anderson

Douglas A Kerns

The multiplier which includes built-in adjustments to improve circuit performance. More specifically, the multiplier is a compensated multiplier to increase the accuracy and precision of computation using analog very large scale integrated (VLSI) circuits and consists of adjustable parameters which allow for the improvement of the linear range of behavior as well as the cancellation of input offsets. A differential multiplier is further described in which adjustable parameters in addition to the four inputs to the multiplier compensate for offsets and non-linearities to result in a highly accurate analog multiplier.

Compensated analog multipliers

A circuit and method for executing real time constraint solution permits real time control of computational tasks using analog very large scale integrated (VLSI) circuits. The constraints of a computation or task are first defined as a function or set of functions. The function(s) are used to produce an error measure function which described how well the constraint(s) is/are stisfied. Analog gradient descent techniques are then used to minimize the error measure function and produce an improved output of the task and optionally adjust the performance of the task. As this is performed in analog VLSI, the constraint solution can be performed continuously and continually in real time, without the limitations of discrete optimization as implemented using digital processing.

Method and apparatus for real-time constraint solution

The circuit generates an output value of an N-dimensional basis function. The circuit includes a string of sub-circuits, each sub-circuit computing a one-dimensional basis function. Each lower dimension sub-circuit is coupled to the adjacent higher dimension circuit, such that the current output is utilized as the input bias current to the adjacent higher dimension circuit. The coupling of sub-circuits in this manner provides the computation of the product of the 1-dimension basis functions produced by each of the sub-circuits.

N-dimensional basis function circuit

A circuit and method for estimating gradients of a target function using noise injection and correlation is provided. In one embodiment, an input signal is combined with an input noise signal and the combined signal is input to a circuit which computes the output of the target function. An amplified noise signal and output signal of the target function are input to a multiplier which performs a correlation of the inputs. The output of the multiplier is processed by a low-pass filter which generates the gradient. The circuit and method can be expanded to N-dimensions. Furthermore, in a alternate embodiment, a differentiator is coupled between the multiplier and amplifier and the multiplier and the output of the target function to differentiate the two signals prior to input to the multiplier. In other embodiments, the circuit may be used to compute gradient-like signals, wherein each component of the gradient is individually scaled by a different value. The output of the circuit can then be used in other descent algorithms. In addition, varying the scale of the noise signal over a time schedule, an annealing style of optimization can be implemented. This prevents the gradient process from stopping at local minima while descending to the global minimum of the function.

Circuit and method for estimating gradients

A system for quadratic and higher order interpolation of pixel color and other pixel values into a bitmap image enables enhanced shading for generation of realistic computer graphics images. The system incorporates modules for executing incremental evaluation of pixel values, utilizing forward differencing in N arbitrary directions of incremental evaluation. The system alternatively incorporates non-incremental evaluation elements for directly evaluating polynomials or executing a spline function of control points.

Quadratic interpolation for shaded image generation

Texture mapping apparatus includes a memory for storing input texture values, interpolators for generating illumination values for sets of display pixels, elements for addressing the memory to generate output texture values, and logic elements for combining the output texture values and the illumination values to generate display color values for each pixel.

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South Pasadena, CA, United States of America

David B Kirk